Mervyn Jones

Engineering education in research-intensive universities

The strengths and weaknesses of engineering education in research-intensive institutions are reported and key areas for developmental focus identified. The work is based on a questionnaire and session summaries used during a two-day international conference held at Imperial College London. The findings highlight several common concerns, such as the need to improve faculty motivation towards teaching, broaden the workplace skills of students, widen employer engagement in teaching and raise the relevance and value of scholarly activity in the discipline of engineering education. Examples of good practice used to address such issues are reported.

Pattern-generation and pattern-transfer for single-digit nano devices

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

Scanning probe lithography approach for beyond CMOS devices

As present CMOS devices approach technological and physical limits at the sub-10 nm scale, a ‘beyond CMOS’ information-processing technology is necessary for timescales beyond the semiconductor technology roadmap. This requires new approaches to logic and memory devices, and to associated lithographic processes. At the sub-5 nm scale, a technology platform based on a combination of high-resolution scanning probe lithography (SPL) and nano-imprint lithography (NIL) is regarded as a promising candidate for both resolution and high throughput production. The practical application of quantum-effect devices, such as room temperature single-electron and quantum-dot devices, then becomes feasible. This paper considers lithographic and device approaches to such a ‘single nanometer manufacturing’ technology. We consider the application of scanning probes, capable of imaging, probing of material properties and lithography at the single nanometer scale. Modified scanning probes are used to pattern molecular glass based resist materials, where the small particle size (<1 nm) and mono-disperse nature leads to more uniform and smaller lithographic pixel size. We also review the current status of single-electron and quantum dot devices capable of room-temperature operation, and discuss the requirements for these devices with regards to practical application.

The influence of hydrostatic pressure on the precipitation of structure-bound water in micro-inclusions in quartz

Abstract The application of a large, hydrostatic, confining pressure to a wet synthetic quartz crystal undergoing heat treatment is shown not to affect significantly the dehydration of the silica structure nor seriously inhibit the growth of fluid-containing micro-inclusions in the crystal.

Resonant tunnelling features in a suspended silicon nanowire single-hole transistor

Suspended silicon nanowires have significant potential for a broad spectrum of device applications. A suspended p-type Si nanowire incorporating Si nanocrystal quantum dots has been used to form a single-hole transistor. Transistor fabrication uses a novel and rapid process, based on focused gallium ion beam exposure and anisotropic wet etching, generating <10 nm nanocrystals inside suspended Si nanowires. Electrical characteristics at 10 K show Coulomb diamonds with charging energy ∼27 meV, associated with a single dominant nanocrystal. Resonant tunnelling features with energy spacing ∼10 meV are observed, parallel to both diamond edges. These may be associated either with excited states or hole–acoustic phonon interactions, in the nanocrystal. In the latter case, the energy spacing corresponds well with reported Raman spectroscopy results and phonon spectra calculations.

Field-emission scanning probe lithography with self-actuating and self-sensing cantilevers for devices with single digit nanometer dimensions

Cost-effective generation of single-digit nano-lithographic features could be the way by which novel nanoelectronic devices, as single electron transistors combined with sophisticated CMOS integrated circuits, can be obtained. The capabilities of Field-Emission Scanning Probe Lithography (FE-SPL) and reactive ion etching (RIE) at cryogenic temperature open up a route to overcome the fundamental size limitations in nanofabrication. FE-SPL employs Fowler-Nordheim electron emission from the tip of a scanning probe in ambient conditions. The energy of the emitted electrons (<100 eV) is close to the lithographically relevant chemical excitations of the resist, thus strongly reducing proximity effects. The use of active, i.e. self-sensing and self-actuated, cantilevers as probes for FE-SPL leads to several promising performance benefits. These include: (1) Closed-loop lithography including pre-imaging, overlay alignment, exposure, and post-imaging for feature inspection; (2) Sub-5-nm lithographic resolution with sub-nm line edge roughness; (3) High overlay alignment accuracy; (4) Relatively low costs of ownership, since no vacuum is needed, and ease-of-use. Thus, FE-SPL is a promising tool for rapid nanoscale prototyping and fabrication of high resolution nanoimprint lithography templates. To demonstrate its capabilities we applied FE-SPL and RIE to fabricate single electron transistors (SET) targeted to operate at room temperature. Electrical characterization of these SET confirmed that the smallest functional structures had a diameter of only 1.8 nanometers. Devices at single digit nano-dimensions contain only a few dopant atoms and thus, these might be used to store and process quantum information by employing the states of individual atoms.

Room-temperature single dopant atom quantum dot transistors in silicon, formed by field-emission scanning probe lithography

Electrical operation of room-temperature (RT) single dopant atom quantum dot (QD) transistors, based on phosphorous atoms isolated within nanoscale SiO2 tunnel barriers, is presented. In contrast to single dopant transistors in silicon, where the QD potential well is shallow and device operation limited to cryogenic temperature, here, a deep (∼2 eV) potential well allows electron confinement at RT. Our transistors use ∼10 nm size scale Si/SiO2/Si point-contact tunnel junctions, defined by scanning probe lithography and geometric oxidation. “Coulomb diamond” charge stability plots are measured at 290 K, with QD addition energy ∼0.3 eV. Theoretical simulation gives a QD size of similar order to the phosphorous atom separation ∼2 nm. Extraction of energy states predicts an anharmonic QD potential, fitted using a Morse oscillator-like potential. The results extend single-atom transistor operation to RT, enable tunneling spectroscopy of impurity atoms in insulators, and allow the energy landscape for P atoms in SiO2 to be determined.Electrical operation of room-temperature (RT) single dopant atom quantum dot (QD) transistors, based on phosphorous atoms isolated within nanoscale SiO2 tunnel barriers, is presented. In contrast to single dopant transistors in silicon, where the QD potential well is shallow and device operation limited to cryogenic temperature, here, a deep (∼2 eV) potential well allows electron confinement at RT. Our transistors use ∼10 nm size scale Si/SiO2/Si point-contact tunnel junctions, defined by scanning probe lithography and geometric oxidation. “Coulomb diamond” charge stability plots are measured at 290 K, with QD addition energy ∼0.3 eV. Theoretical simulation gives a QD size of similar order to the phosphorous atom separation ∼2 nm. Extraction of energy states predicts an anharmonic QD potential, fitted using a Morse oscillator-like potential. The results extend single-atom transistor operation to RT, enable ...