Michael A. Ruegg

A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch

A fully integrated ring oscillator PLL for hard disk channel applications is presented. A number of 16 equidistant phases of the output clock, programmable in 0.4% steps between 200 MHz and 2.5 GHz are achieved by the use of a phase-switching fractional N architecture. Phase mismatch is optimized by the use of a novel two delay stage ring oscillator running at 4/spl times/ output frequency (800 MHz-10 GHz) and a subsequent divider chain. Jitter and area consumption are improved by solely controlling the VCO via its power supply. The proposed VCOs jitter/power/number of stages relationship behaves analogue to a single ended structure although the ring delivers 4 differential clock phases. The PLL was built in standard 0.12 /spl mu/m CMOS technology. It achieves a phase noise performance of -96 dBc/Hz @ 1 MHz offset on a 1.6 GHz signal. The integrated jitter in the measured band (10 kHz-10 MHz) is 3.8 ps. The PLL consumes 0.06 mm/sup 2/ only.