Michael C. Shebanow

Processor structure and method for renamable trap-stack

Method and apparatus for register management using issue sequence prior physical register and register association validity information

Computer and error recovery method for the same

Method and apparatus for rotating active instructions in a parallel data processor

Addressing method for executing load instructions out of order with respect to store instructions

Structure and method for instruction boundary machine state restoration

Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation

Method and apparatus for selecting the oldest queued instructions without data dependencies

Method and apparatus for coordinating the use of physical registers in a microprocessor

Superscalar processor with multiple register windows and speculative return address generation