Hideki Osone

A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Maximum baud rate of electrical signaling over backplanes is limited by reflection and crosstalk noise at connectors as well as ISI caused by frequency-dependent dielectric loss. A DFE is an effective circuit to alleviate ISI without amplifying noise. A multi-tap DFE is often used in order to cancel long-tail ISI [1–3]. However, multiple DFE taps may limit maximum operation speed due to analog feedback when using non-speculative taps [1,2], or increase power and area exponentially when using multiple speculative taps [3]. Another approach is a combination of a 1-tap speculative DFE to get faster speed and a linear equalizer (LE) to cancel the long-tail ISI [4,5]. Adaptive control is challenging when combining LE and DFE, because the relationship between LE and DFE must be taken into account [5], and the sign-sign-least-mean-square (SS-LMS) algorithm [7] that is commonly used in DFEs is not applicable to some types of LE, or at the cost of increased power and area for parallel signal paths in LE [6]. The zero-forcing (ZF) algorithm for analog filters [8] is applicable to any type of LE, but it needs an ADC and a large amount of logic to perform matrix multiplication. A heuristic algorithm [5] requires an eye measurement circuit, microcontroller, and control software.

Error detection and handling in a superscalar, speculative out-of-order execution processor system

The HaL SPARC64 Processor, the first 64-bit SPARC-V9 architecture implementation, uses several techniques to ensure a high degree of system reliability, error detection, and error recovery. The CPU of the multi-chip module processor has a superscalar, speculative issue unit, and an out-of-order execution datapath. These two processor components complicate the maintenance of precise state in the event of errors. By exploiting the SPARC-V9 architectural features, and the micro-architecture for speculative execution, SPARC64 maintains precise state in the event of exceptions and errors, logs and reports errors, and facilitates error detection during full system bringup. The paper presents details of error detection and handling in the CPU, the cache system, and the Memory Management Unit(MMU). The HaL R1 system also implements a fault-secure memory system design. The memory system corrects all single-bit errors, detects double bit errors, detects single address line failures, and detects all single dynamic RAM (DRAM) chip failures. Certain debug features have been added to the system that are useful during system bring-up.<<ETX>>

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

Fabricated in 90nm CMOS, the chip consumes 545mW and has a pattern-balancing adaptive equalizer that is stable for any data patterns including those with a strong peak component at a single frequency. The adaptive equalizer yields a gain at fs/2 relative to fs/16 varying from -1.7 to 2.2dB for any 8B10B encoded Ethernet frames filled with a fixed data byte

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel

In multi-Gb/s wireline communications, equalizers are used to compensate for channel-induced signal distortion in order to stretch the maximum distance of transmission. Both amplitude and phase can be distorted in a channel. Amplitude distortion is a frequency-dependent attenuation due to skin effect and dielectric loss, causing inter-symbol-interference (ISI). A transmitter (TX) discrete-time pre-emphasis (PE) filter, a receiver (RX) continuous-time Linear Equalizer (LE), and an RX Decision-Feedback Equalizer (DFE) are generally used to cancel ISI. At 10Gb/s or higher data rate, equalizers for up to 33 to 39dB Nyquist loss and up to 20 to 25dB adapted loss range were reported [1–3]. On the other hand, how to compensate phase distortion is not clearly understood in practical circuit design. Theoretically, if a channel has minimum-phase-likecharacteristics, phase distortion is automatically co-equalized with amplitude distortion by a minimum-phase equalizer [4]. While this is the case for high-speed cables [5], it is not for PCB traces, because a non-minimum-phase equalizer, e.g., a PE with a pre-cursor tap, produces lower BER over a high-loss PCB channel than a minimum-phase equalizer, e.g., a PE without a pre-cursor tap. Thus the IEEE 10Gb Ethernet standard for backplanes adopted 3-tap PE with a precursor tap [6]. However, adaptive phase equalization in hardware has not been reported in the literature.

A 4-channel 3.125Gb/s/ch CMOS transceiver with 30dB equalization

A 4-channel 3.125Gb/s/ch CMOS transceiver has been developed. The receiver includes a second-order derivative analog equalizer to compensate the frequency-dependent attenuation. Equalization can be performed adaptively through monitoring the residual inter-symbol-interference. To talk with a system without receiver equalization, a multiple-tap filter for pre-emphasis is implemented in transmitter. Either analog filter or pre-emphasis is capable of 30dB equalization. Transceiver design is compatible with XAUI and 10GBASE-CX4, but extending the reach over copper cabling. Evaluation shows lower than 10/sup -12/ BER has been achieved with 30-meter AWG 24 cable.

Gain-phase co-equalization for widely-used high-speed cables

Based on observation that widely-used high-speed cables have minimum-phase-like characteristics, we developed a minimum-phase equalizer, which is optimal for such cables. An analog 2/sup nd/-order derivative equalizer was employed, and our analysis showed positive coefficients are needed to make it minimum-phase. Since the equalizer is minimum-phase, phase is automatically equalized when gain is equalized enough. The equalizer was implemented in 0.11/spl mu/m CMOS technology, and measurement showed BER < 10/sup -12/ with a 40m AWG24 InfiniBand cable at 3.125Gbaud.

Design Consideration of 6.25 Gbps Signaling for High-Performance Server

As network data rate increases rapidly, high-speed signaling circuits for server communication pose many design challenges due to various system requirements using different interconnect mediums. This paper discusses main problems and solutions of high-speed circuits for server interconnect. Then, it presents a high-speed circuit implementation for such interconnect using 90nm CMOS technology that achieved data rate at 6.25 Gbps in a backplane environment.