Michael Heer

Thermal imaging of smart power DMOS transistors in the thermally unstable regime using a compact transient interferometric mapping system

Smart power DMOSes are analyzed under thermally unstable conditions up to the destruction level using a new compact version of the transient interferometric mapping (TIM) method. High accuracy phase measurements are achieved employing superluminescent diodes and focal plane array cameras. Two-dimensional thermal mapping at two time instants during a single stress pulse is performed in the range of 100 μs to few milliseconds. The size of the region where the parasitic bipolar transistor becomes thermally activated at the onset of thermal runaway is determined. The results are correlated to conventional failure analysis.

External (transient) latchup phenomenon investigated by optical mapping (TIM) technique

Substrate current distribution as trigger for external latchup (LU) and transient latchup (TLU) is detected successfully by means of optical transient interferometric mapping (TIM) technique. The substrate current flow is studied on transient base and for various guard-ring configurations. TIM uncovers proximity effects causing substrate current crowding which are important for the definition of LU protection concepts.

Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up

Current flow uniformity during ESD induced latch-up event is investigated in multi-finger LDMOS clamps and SCR ESD protection devices fabricated in a 0.6 μm high voltage CMOS process. Current flow, excess free carrier and hot spot distribution are analyzed by transient interferometric mapping technique combined with a latch-up pulse system consisting of a solid state pulser and a clear pulse unit. During latch-up, the current in the LDMOS clamps flows just in a single spot and the failure position is random and independent on device type. The position of the failure site correlates with the trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in the current flow.

Hot spot analysis during thermal shutdown of SOI BCDMOS half bridge driver for automotive applications

Abstract The thermal distribution in large DMOS output transistors of a half-bridge driver IC fabricated in smart-power SOI technology is investigated by the backside transient interferometric mapping (TIM) technique during its thermal shutdown process. The TIM measurements uncovers four hot spots, where the temperature exceeds the limit of the built in temperature sensor. This explains the specific failure mode which was identified during accelerated reliability tests. The TIM results are complemented by temperature measurements with the build-in temperature sensors.

Experimental and numerical analysis of current flow homogeneity in low voltage SOI multi-finger gg-NMOS and NPN ESD protection devices.

Triggering uniformity and current sharing under TLP stress is investigated in low voltage multi-finger gg-NMOS and NPN ESD protection devices fabricated in smart-power SOI technology. Inhomogeneous current distribution over the fingers and within a single finger is detected by the backside transient interferometric mapping (TIM) technique. 2D TCAD device simulations of the multi-finger devices are used to explain the experimental TIM results. Changes in differential resistance in the pulsed IV characteristics of the NPN ESD protection devices are also explained by TIM experiments.

Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology.

Substrate current distribution as trigger for external latch-up (LU) and transient latch-up (TLU) is analyzed by optical transient interferometric mapping (TIM) technique. The transient free carrier (plasma) concentration related to substrate current flow is studied for various guard-ring configurations and injection carrier type on special test structures and real I/O cells. TIM uncovers proximity effects in I/O cells causing substrate current crowding which are important for the definition of effective LU protection concepts.

Automated setup for thermal imaging and electrical degradation study of power DMOS devices

An automated setup for investigation of degradation mechanisms in semiconductor devices under electrostatic discharge (ESD) stress is presented. Vertical-DMOS transistors of a Smart Power technology operating in bipolar snapback mode are studied by combined techniques. The current filamentary behavior imaged by a two-instants transient interferometric mapping (TIM) method and the variation of device DC characteristics are studied as a function of stress current. During repeated stress, a progressive degradation of the DC leakage current at the failure level and a slight gradual change of transfer characteristics are observed. The failure location, resolved in three dimensions by backside infrared microscopy, agrees with the position obtained from the TIM analysis and expected from device physics.