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Dive into the research topics where Michael Joseph Mcpartlin is active.

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Featured researches published by Michael Joseph Mcpartlin.


IEEE Microwave and Wireless Components Letters | 2012

A 5 GHz 0.95 dB NF Highly Linear Cascode Floating-Body LNA in 180 nm SOI CMOS Technology

Anuj Madan; Michael Joseph Mcpartlin; Christophe Masse; William Vaillancourt; John D. Cressler

A 5 GHz CMOS LNA featuring a record 0.95 dB noise-figure is reported. Using an inductively-degenerated cascode topology combined with floating-body transistors and high-Q passives on an SOI substrate, record noise figure and superior linearity performance at 5 GHz are obtained. The low-noise amplifier (LNA) achieves up to 11 dB of gain while consuming 12 mW dc power, and is capable of supporting 802.11a WLAN applications. The impact of SOI body-contact on the LNA RF performance is described and linked to improved intermodulation performance.


IEEE Journal of Solid-state Circuits | 2011

Fully Integrated Switch-LNA Front-End IC Design in CMOS: A Systematic Approach for WLAN

Anuj Madan; Michael Joseph Mcpartlin; Zhan-Feng Zhou; Chun-Wen Paul Huang; Christophe Masse; John D. Cressler

A fully integrated front-end IC is demonstrated for 802.11b/g transceivers with integrated power amplifiers. The SP3T-LNA architecture integrates Bluetooth® functionality with transmit and receive for wireless LAN. The transmit switch achieves a P1dB greater than 33.0 dBm at 2.5 GHz by employing a cross-biasing approach, transistor stacking and deep n-well process. Power handling techniques used for the switches and the associated performance tradeoffs are discussed. The measured noise figure of the LNA and the receive chain comprising both an LNA and a switch is 1.5 dB and 3.0 dB, respectively. The LNA achieves an IIP3 of 7.0 dBm while consuming 7.0 mA of current. The measured switching times are less than 350 ns. The front-end IC employs a 3.3 V supply and occupies 0.64 mm2 in 0.18 μm bulk CMOS technology.


bipolar/bicmos circuits and technology meeting | 2007

Large Signal Modeling of High Efficiency SiGe HBTs for Power Amplifier Applications

Ramana M. Malladi; Michael Joseph Mcpartlin; Alvin J. Joseph; Hugues Lafontaine; Mark Doherty

Large-signal compact modeling of SiGe HBTs integrated into a new IBM BICMOS technology geared towards high-efficiency power amplifiers is described. The technology exhibits a record 73% PAE at 5.75 GHz in class AB operation. A scalable HiCUM model (high current model) is developed to accurately model the DC, small-signal and large-signal characteristics. Results of DC, fT characteristics, output power, PAE and AM-PM performance of the device are discussed in detail.


Archive | 2004

Integrated power amplifier circuit

Mark Doherty; John Gillis; Michael Joseph Mcpartlin; David Helms; Phillip Antognetti


Archive | 2013

BIPOLAR TRANSISTOR ON HIGH-RESISTIVITY SUBSTRATE

Michael Joseph Mcpartlin; Mark Doherty


Archive | 2015

Integrated RF front end system

Michael Joseph Mcpartlin; Mark Doherty


Archive | 2014

FET TRANSISTOR ON HIGH-RESISTIVITY SUBSTRATE

Michael Joseph Mcpartlin


Archive | 2014

DEVICE MANUFACTURING USING HIGH-RESISTIVITY BULK SILICON WAFER

Michael Joseph Mcpartlin


Archive | 2014

SEMICONDUCTOR SUBSTRATE HAVING HIGH AND LOW-RESISTIVITY PORTIONS

Michael Joseph Mcpartlin


Archive | 2009

Integrated Circuit with Improved Transmission Line Structure and Electromagnetic Shielding Between Radio Frequency Circuit Paths

Mark Doherty; Michael Joseph Mcpartlin; Chun-Wen Paul Huang

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John D. Cressler

Georgia Institute of Technology

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