Michael L. Lovejoy

Temperature dependence of minority and majority carrier mobilities in degenerately doped GaAs

Measured minority and majority carrier mobility temperature dependencies in heavily doped n‐ and p‐GaAs are compared. Majority carrier mobilities in heavily doped GaAs are essentially temperature (T) independent while minority carrier mobilities exhibit a roughly 1/T dependence. Majority carrier freezeout, which reduces both majority–minority carrier and ionized impurity scattering, is shown not to be responsible for the 1/T minority carrier mobility dependence. The difference in minority and majority carrier mobility T dependencies is explained in terms of the increased degree of degeneracy of majority carriers with decreased temperature, which decreases majority–minority carrier scattering.

Thin-film tantalum-nitride resistor technology for phosphide-based optoelectronics

Abstract The phosphide material system is an important material system for both microelectronics and optoelectronics, but integrated circuit technology on InP substrates is immature. In this work, thin-film deposition techniques and resistor processing techniques to fabricate fine-line geometry resistors for InP-based electronics are reported. Deposition parameters for d.c. reactive sputtering of tantalum in an argon-nitrogen ambient to realize tantalum nitride thin films with 50 Ωp[ sheet resistance are optimized. The dependence of electrical properties, including resistivity, Seebeck ratio and temperature coefficient of resistivity, are reported for a wide range of nitrogen flow. In common with other electronic material systems, Seebeck ratio characterization is implemented for process control monitoring of phosphide-based electronics fabrication. Material composition as a function of nitrogen flow is determined by Rutherford backscattering and elastic recoil detection. Techniques to fabricate low resistance contacts to the TaN are discussed. The processes are demonstrated with the fabrication of high-density, two-dimensional arrays of photoreceivers based on amplifiers using the tantalum nitrate resistor technology.

Plasma‐induced damage of GaAs during etching of refractory metal contacts

The effect of plasma‐induced damage on the majority carrier transport properties of p‐type GaAs has been studied by monitoring changes in sheet resistance (Rs) of thin conducting layers under various plasma conditions including etch conditions for refractory metal contacts. Rs determined from transmission line measurements are used to evaluate plasma‐induced damage for electron cyclotron resonance (ECR) and reactive ion etch (RIE) conditions by varying the thickness and doping of epitaxial layers. Damage depths calculated from Rs data show a strong dependence on doping levels. This can be explained by a plasma‐damage‐induced trap density profile which tails off into the sample. Consistent trends have been observed where Rs increases with increasing dc bias, increasing microwave power, and decreasing pressure, thus showing Rs increases as either the ion energy or ion flux increases. The lowest plasma‐induced damage observed in this study occurs with ECR at low microwave power and no rf biasing. Under rf‐bi...

Low-power modular parallel photonic data links

Many of the potential applications for parallel photonic data links could benefit from a bi-directional Optoelectronic Multi-Chip Module (OEMCM), where the optical transmitter, receiver, and first-level interface electronics are combined into a single package. It would be desirable for such a module to exhibit low power consumption, have a simple electronic interface that can operate at a variety of speeds and possess a capability to use interchangeable optics for a variety of external connections. Here, we describe initial results for a parallel photonic link technology that exhibits those properties. This link uses high-efficiency, back-emitting, two-dimensional Vertical Cavity Surface-Emitting Laser (VCSEL) arrays operating at 980 nm. The lasers are matched, via integrated microlenses, to corresponding monolithically-integrated photoreceiver arrays that are constructed in a InGaAs/InP Heterojunction Bipolar Transistor (HBT) technology. In initial breadboard-level tests, the photonic data channels built with these devices have been demonstrated with direct (3.3 V) CMOS drive of the VCSELs and a corresponding CMOS interface at the photoreceiver outputs. These links have shown electrical power consumption as low as 42 mW per channel for a 50% average duty cycle while operating at 100 Mb/s.

INVESTIGATION OF PLASMA ETCH INDUCED DAMAGE IN COMPOUND SEMICONDUCTOR DEVICES

We have investigated the electrical performance of mesa‐isolated GaAs pn‐junction diodes to determine the plasma‐induced damage effects from reactive ion and reactive ion beam etching (RIBE). A variety of plasma chemistries (SiCl4, BCl3, BCl3/Cl2, and Cl2) and ion energies ranging from 100 to 400 eV were studied. We have observed that many of the reactive ion etching BCl3/Cl2 plasmas and RIBE Cl2 plasmas yield diodes with low reverse‐bias currents that are comparable to the electrical characteristics of wet‐chemical‐etched devices. The reverse‐bias leakage currents are independent of surface morphology and sidewall profiles.

Low-power approaches for parallel free-space photonic interconnects

Future advances in the application of photonic interconnects will involve the insertion of parallel-channel links into Multi-Chip Modules (MCMs) and board-level parallel connections. Such applications will drive photonic link components into more compact forms that consume far less power than traditional telecommunication data links. These will make use of new device-level technologies such as vertical cavity surfaceemitting lasers and special low-power parallel photoreceiver circuits. Depending on the application, these device technologies will often be monolithically integrated to reduce the amount of board or module real estate required by the photonics. Highly parallel MCM and board-level applications will also require simplified drive circuitry, lower cost, and higher reliability than has been demonstrated in photonic and optoelectronic technologies. An example is found in two-dimensional point-to-point array interconnects for MCM stacking. These interconnects are based on high-efficiency Vertical Cavity Surface Emitting Lasers (VCSELs), Heterojunction Bipolar Transistor (HBT) photoreceivers, integrated micro-optics, and MCM-compatible packaging techniques. Individual channels have been demonstrated at 100 Mb/s, operating with a direct 3.3V CMOS electronic interface while using 45 mW of electrical power. These results demonstrate how optoelectronic device technologies can be optimized for low-power parallel link applications.

Low-power, parallel photonic interconnections for multi-chip module applications

New applications of photonic interconnects will involve the insertion of parallel-channel links into Multi-Chip Modules (MCMs). Such applications will drive photonic link components into more compact forms that consume far less power than traditional telecommunication data links. MCM-based applications will also require simplified drive circuitry, lower cost, and higher reliability than has been demonstrated currently in photonic and optoelectronic technologies. The work described is a parallel link array, designed for vertical (Z-Axis) interconnection of the layers in a MCM-based signal processor stack, operating at a data rate of 100 Mb/s. This interconnect is based upon high-efficiency VCSELs, HBT photoreceivers, integrated micro-optics, and MCM-compatible packaging techniques.

Low-power, high-speed InGaAs/InP photoreceiver for highly-parallel optical data links

Low-power photoreceivers based on InGaAs/InP heterojunction bipolar transistors (HBTs) and p-i-n diodes for highly-parallel optical data links have been designed, fabricated and characterized. The receivers are designed to operate from 980 nm to over 1.3 /spl mu/m and interface directly with 3.3 V CMOS. SPICE was utilized to investigate circuit topographies that minimize power dissipation while maintaining large signal operation required to interface directly with CMOS. Low-power dissipation of /spl sim/10 mW/channel has been achieved at bit rates up to 800 Mbits/sec. Performance characteristics of discrete HBTs and of low-power photoreceivers fabricated with p-i-n/HBT circuits are reported.

Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

Future manufacturing techniques for stacked MCM interconnections

As multichip modules (MCMs) grow in chip count and complexity, increasingly large numbers of input/output (I/O) channels will be required for connection to other MCMs or printed wiring boards. In applications such as digital signal processing, large increases in processing density (number of operations in a given volume) can be obtained in stacked MCM arrangements. The potential pin counts and required I/O densities in these stacked architectures will push beyond the limits of present interlevel coupling techniques. This problem is particularly acute if easy separation of layers is needed to meet MCM testing and yield requirements. Solutions to this problem include the use of laser-drilled, metal-filled electrical vias in the MCM substrate and also optoelectronic data channels that operate in large arrays. These arrays will emit and detect signals traveling perpendicular to the surface of the MCM. All of these approaches will require packaging and alignment that makes use of advanced MCM manufacturing techniques.