Michael Pike

New ESCAP-type resist with enhanced etch resistance and its application to future DRAM and logic devices

This new photoresist system extends the capability of the ESCAP platform previously discussed. (1) This resist material features a modified ESCAP type 4-hydroxystyrene-t-butyl acrylate polymer system which is capable of annealing due to the increased stability of the t-butyl ester blocking group. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus previous DUV resists, APEX and UV2HS. Improved stabilization of chemically amplified photoresist images can be achieved through reduction of film volume by film densification. When the host polymer provides good thermal stability the soft bake conditions can be above or near the Tg (glass transition) temperature of the polymer. The concept of annealing (film densification) can significantly improve the environmental stability of the photoresist system. Improvements in the photoacid generator, processing conditions and overall formulation coupled with high NA (numerical aperture) exposure systems, affords linear lithography down to 0.15 micrometer for isolated lines with excellent post exposure delay stability. In this paper, we discuss the UV4 and UV5 photoresist systems based on the ESCAP materials platform. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus APEX-E and UV2HS. Due to lower acrylate content, the Rmax for this system can be tuned for feature-type optimization. We demonstrate sub-0.25 micrometer process window for isolated lines using these resists on a conventional exposure tool with chrome on glass masks. We also discuss current use for various device levels including gate structures for advanced microprocessor designs. Additional data will be provided on advanced DRAM applications for 0.25 micrometer and sub-0.25 micrometer programs.

The GridMapper challenge: how to integrate into manufacturing for reduced overlay error

More sophisticated corrections of overlay error are required because of the challenge caused by technology scaling faster than fundamental tool improvements. Starting at the 45 nm node, the gap between the matchedmachine- overlay error (MMO) and technology requirement has decreased to the point where additional overlay correction methods are needed. This paper focuses on the steps we have taken to enable GridMapperTM, which is offered by ASML, as a method to reduce overlay error. The paper reviews the basic challenges of overlay error and previous standard correction practices. It then describes implementation of GridMapper into IBMs 300 mm fabrication facility. This paper also describes the challenges we faced and the improvements in overlay control observed with the use of this technique. Specifically, this paper will illustrate several improvements: 1. Minimization of non-linear grid signature differences between tools 2. Optimization of overlay corrections across all fields 3. Decreased grid errors, even on levels not using GridMapper 4. Maintenance of the grid for the lifetime of a product 5. Effectiveness in manufacturing - cycle time, automated corrections for tool grid signature changes and overlay performance similar to dedicated chuck performance

High-order wafer alignment in manufacturing

Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes. Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated. How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product specific corrections per exposure and 10 term APC process control.

Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Cr migration on 193nm binary photomasks

A new type of chrome-on-glass (COG) photomask defect was observed in 2006. Absorber material migrated into vias on dark field masks, partially obscuring the incident 193nm light and thereby causing the imaged photoresist to be underexposed. Through detailed characterization of new and defective photomasks and their histories it was determined that the migration is not caused by any unusual line events or faulty mask handling procedures. Rather, it is an inevitable result of mask use under specific conditions. Four essential elements have been identified: the presence of Cr, 193nm light exposure, charge, and water vapor and their roles elucidated through modeling studies and existing literature. We have reproduced Cr migration in the laboratory, demonstrating that these four elements are necessary and sufficient for this type of defect to occur. The only way to avoid Cr migration is to avoid reactions with water vapor.

Effects of intra chip topography in back end of line processes on focus leveling control and process window degradation with high NA exposures

Modern High NA exposure systems trade off process depth of focus for gains in image resolution. The ever increasing Lens NA and associated loss of process window put greater demands on focus and leveling control as well as product design in order to gain back process capability. Poor chip design combined with multi level Back End of Line structures can create local topographies that exceed the focus budget of a modern High NA lens. The impact of these complications can be a significantly narrowed process window and increased ACLV. Advanced multi-point focusing and die-by-die leveling methods attempt to gain back focus window lost due to increased lens NA and wafer topography. In this paper we correlate surface topography and chip design to focus and leveling problems. Step height differences between Kerf and product surfaces were measured using AFM. Leveling tilts and effect on DOF were evaluated using FEM methods. ASML leveling metrology methods such as Dynamic Leveling, Local Offset Profile, Static Local Leveling, Static Global Leveling, and the use of Fixed Leveling Offsets were evaluated with respect to improving process windows and ACLV.

Intra-field overlay correction for illumination based distortion

The use of extreme freeform illumination conditions and multi patterning processes used to generate sub 40nm images can result in significant intra-field overlay errors. When levels with differing illumination conditions are aligned to each other, these intra-field distortions can result in overlay errors which are uncorrectable using normal linear feedback corrections. We use a double exposure method, previously described by Minghetti [1] et al. to isolate and measure intra-field overlay distortions caused by tool lens signatures and different illumination conditions. A full field test reticle is used to create a dual level expose pattern. The same pattern is exposed twice, but with two different illumination conditions. The first exposure is done with a standard reference illumination. The second exposure is the target illumination condition. The test reticle has overlay target pairs that are measurable when the 2nd exposure is offset in the Y direction by the designed amount. This allows for a high density, 13x13, intra-field overlay measurement to be collected and modeled to determine 2nd and 3rd order intra-field terms. Since the resulting illumination and scanner lens specific intra field corrections are independent of field size, the sub-recipes can be applied to any product exposure independent of field size, which use the same illumination conditions as the test exposures. When the method is applied to all exposure levels in a product build cycle, the overlay errors contributed by the reference illumination condition cancel out. The remaining errors are due exclusively to the impact of the illumination condition on that scanner lens. Actual results correlated well with the model with more than 80% of the predicted overlay improvement being achieved.

Advanced overlay control in volume manufacturing

The work reviewed will describe a particular effort in the area of overlay matching based on the BaseLiner™ package marketed by ASML. BaseLiner relies on the concept of Scanner Baseline Constants (SBCs). Traditionally, optical lithography systems are controlled by many numerical parameters known as Machine Constants (MCs). MCs are typically generated by a lithography system during in situ or other system based tests that generate and optimize the MCs for a very specific test condition set. The concept of SBCs introduces a “middle layer” of offsets that forces tools to be closely matched to one another under general lithography conditions, not just the specific test conditions used for MC generation. The methodology is designed to handle specific product layouts.