Christopher P. Ausschnitt

Quantitative stepper metrology using the focus monitor test mask

A new lithographic test pattern, the focus monitor, is introduced. Through the use of phase shift techniques, focus errors translate into easily measurable overlay shifts in the printed pattern. Each individual focus monitor pattern can be directly read for the sign and magnitude of the focus error. This paper presents a detailed verification of the validity of this approach, along with several preliminary applications.

A New Approach to Pattern Metrology

We describe an approach to pattern metrology that enables the simultaneous determination of critical dimensions, overlay and film thickness. A single optical system captures nonzero- and zero-order diffracted signals from illuminated grating targets, as well as unpatterned regions of the surrounding substrate. Differential targets provide in situ dimensional calibration. CD target signals are analyzed to determine average dimension, profile attributes, and effective dose and defocus. In turn, effective dose and defocus determines all CDs pre-correlated to the dose and focus settings of the exposure tool. Overlay target signals are analyzed to determine the relative reflectivity of the layer pair and the overlay error between them. Compared to commercially available pattern metrology (SEM, optical microscopy, AFM, scatterometry and schnitzlometry), our approach promises improved signal-to-noise, higher throughput and smaller targets. We have dubbed this optical chimera MOXIE (Metrology Of eXtremely Irrational Exuberance).

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Modeling for profile-based process-window metrology

We formulate a physical model to extract effective dose and defocus (EDD) from pattern profile data and demonstrate its efficacy in the analysis of in-line scatterometer measurements. From the measurement of a single target structure, the model enables simultaneous computation of pattern dimensions pre-calibrated to the imaging system dose and focus settings. Our approach is generally applicable to ensuring the adherence of pattern features to dimensional tolerances in the control and disposition of product wafers while minimizing in-line metrology.

Advanced DUV photolithography in a pilot line environment

As the critical path to increasing circuit density, deep-ultraviolet (DUV) lithography has played a key role in the development of new semiconductor products. At present, DUV refers to imagery at the 248-nm wavelength, with the introduction of 193-nm photolithographic systems anticipated in the next few years. This paper presents an overview of DUV lithography applications in the IBM Advanced Semiconductor Technology Center (ASTC). Since 1990, we have used DUV lithography for critical levels of advanced generations of DRAM (64Mb, 256Mb, and 1Gb) and associated families of logic products. We describe the means by which DUV capability and productivity have increased in a decreasing process window environment. Tooling, processes, and process control systems have undergone continuous improvement to accommodate increasing wafer starts and the rapid introduction of new products.

Distinguishing dose from defocus for in-line lithography control

Manufacturing control of a lithographic process must guarantee that the pattern features on a masking level stay within a common process window, the focus-exposure space over which all pattern tolerances are met. To do so at focus latitudes below 1 micrometers , simultaneous determination and correction of dose and defocus error is required. In-line metrology practice has been to measure a single pattern attribute, usually the dimension of the smallest feature, at each of several locations on a wafer. Since the measurement of one pattern attribute, regardless of its accuracy or precision, cannot distinguish two variables - this approach is inherently inadequate for lithography control. We demonstrate how dose and defocus can be derived from the attributes of dual-tone, optically measurable targets on product wafers. Our method is applied to the in-line control of sub-0.25 micrometers step-and-scan lithography.

Process monitor gratings

Despite the increasing use of advanced imaging methods to pattern chip features, process windows continue to shrink with decreasing critical dimensions. Controlling the manufacturing process within these shrinking windows requires monitor structures designed to maximize both sensitivity and robustness. In particular, monitor structures must exhibit a large, measurable response to dose and focus changes over the entire range of the critical features process window. Any process variations present fundamental challenges to the effectiveness of OPC methods, since the shape compensation assumes a repeatable process. One particular process parameter which is under increasing scrutiny is focus blur, e.g. from finite laser bandwidth, which can cause such OPC instability, and thereby damage pattern fidelity. We introduce a new type of test target called the Process Monitor Grating (PMG) which is designed for extreme sensitivity to process variation. The PMG design principle is to use assist features to zero out higher diffraction orders. We show via simulation and experiment that such structures are indeed very sensitive to process variation. In addition, PMG targets have other desirable attributes such as mask manufacturability, robustness to pattern collapse, and compatibility with standard CD metrology methods such as scatterometry. PMG targets are applicable to the accurate determination of dose and focus deviations, and in combination with an isofocal grating target, allow the accurate determination of focus blur. The methods shown in this paper are broadly applicable to the characterization of process deviations using test wafers or to the control of product using kerf structures.

Multi-Patterning Overlay Control

The extension of optical lithography to 32nm and beyond is dependent on double-patterning (DP) at critical levels. DP integration strategies result in added degrees of freedom for overlay variation. In particular, overlay control requires assessment of error among various mask/level combinations. The Blossom overlay metrology approach minimizes the size of the overlay marks associated with each mask/level while maximizing the density of marks within the overlay metrology tools field of view (FOV). We examine Blossom enabled use cases in DP lithography control; specifically, within-field and multiple mask/level sampling.

Blossom overlay metrology implementation

Improved overlay capability and sampling to control advanced lithography has accelerated the need for compact, multilayer/ mask/field/mark overlay metrology. The Blossom approach minimizes the size of the overlay marks associated with each layer while maximizing the density of marks within the overlay metrology tools field of view (FOV). Here we describe our progress implementing this approach in 45nm manufacturing.

Smaller, smarter, faster, and more accurate: the new overlay metrology

With the introduction of double patterning, overlay capability below 5nm is required for optical lithography density scaling to the 22nm node and beyond. Commensurate overlay metrology must enable dense sampling of all patterned area to control single-nanometer systematic sources of error among an increasing number of device layers. This translates to the need for sub-second measurement of microscopic targets representing multiple layers within a metrology tool field of view, all while improving accuracy. Blossom (BLO) is the overlay metrology of record for the IBM 32nm technology. As we will describe here, the densely packed array of layers represented in a single BLO target has enabled us to conduct within-field in-line sampling on our most critical layers. We will also report the significant improvements to metrology performance that have resulted from our migration of BLO technology to a new measurement platform. In addition, as 22nm development proceeds, we are shrinking our overlay targets further. A target suitable for within-chip insertion, a 10μm square micro-Blossom (μBLO) target, can accommodate up to 8 layers. Correlation of μBLO to BLO measurements on a layer pair shows excellent agreement, and despite an approximately 10X area shrink relative to BLO, the μBLO measurement uncertainty remains comfortably below 0.5nm. Our paper presents details of our target layout, measurement, and analysis approach. In addition, we detail data representative of overlay variation in state-of-the-art lithographic processes, along with our outlook for overlay metrology implementation for future technologies.