Michael Stoisiek

Origin of 1/f noise in bipolar transistors

In planar n-p-n transistors fabricated in IC technology, the dependence of 1/<tex>f</tex>noise on the base current density j<inf>B</inf>, the base width W<inf>B</inf>, and the emitter area F<inf>E</inf>was measured. The power spectrum<tex>S_{iB}(f)</tex>of the base current fluctuations i<inf>B</inf>can be represented by the empirical relation<tex>S_{iB} = const. j\min{B}\max{\gamma} \cdot F\min{E}\max{\beta} \cdot w\min{B}\max{-1} \cdot f^{-1}</tex>where<tex>1 \leq \gamma \leq 2</tex>and β has been found to be 1.3 or 2. The results of measurements on gate-controlled devices indicate that 1/<tex>f</tex>noise cannot be explained by McWhorters surface model. Therefore, a new model is proposed which assumes resistance fluctuations in the base region as the cause of 1/<tex>f</tex>noise in bipolar transistors. The model establishes the relation for<tex>S_{iB}(f)</tex>as well as the magnitude of the coefficients β and γ.

A 200-A/2000-V MOS-GTO with improved cell design

A large-area MOS-controlled thyristor (MOS-GTO) has been realized by introducing a new wafer-scale repair technique. The large-area device has a diameter of 3 cm. It has been contacted with an IC-compatible pressure contact and has been fabricated on a lowly doped n-type substrate suitable for very-high-voltage applications comparable to conventional GTOs. The snubbered and unsnubbered turn-off currents were 400 and 200 A, respectively. The currents could be switched up to a final anode-to-cathode voltage of >1500 V. The unique turn-off capabilities have been achieved by an improved design of the MOS-controlled emitter cell. The main feature of the new cell design is an integrated emitter series resistor, which avoids current filamentation during turn-off. In addition an n/sup +/ buried layer underneath the source of the MOS-controlled emitter cell has been used to reduce the parasitic action of the MOS part of the emitter cell during the on-state. >

A dielectric isolated high-voltage IC-technology for off-line applications

The paper reports a first attempt to a dielectric isolated 600 V IC-process. With commercially available direct-wafer-bonded Si/SiO/sub 2//Si-wafers we processed the isolated islands with the basic high voltage devices in a standard sub-/spl mu/ fabrication line. For the lateral isolation we used a deep trench etch- and refill process. Experimental results for lateral high voltage DMOS (LDMOS), and p-MOS transistors (HVPMOS) as well as lateral IGBTs (LIGBT) and diodes are in good agreement with the target values. The suitability of the process concept for the intended applications is shown with an IGBT half-bridge demonstrator.

A large area MOS-GTO with wafer-repair technique

Turn-off thyristors with MOS-controlled emitter-base shorts (MOS-GTOs) are fabricated by using IC technology. Therefore, the device area is limited to about 1 cm2. However, typical power devices for currents >100 amps need to have areas well above this value. We now succeeded in realizing a MOS-GTO of 3 cm diameter by applying a laboratory type wafer repair technique. Processing failures, like shorts of some kind, are treated in a way which keeps this failures electrical inactive. These devices are comparable to conventional thyristors in their on-state and blocking behaviour. Turn-off currents of about 700 amps can be achieved at low anode-voltages. However, at high anode-voltages the turnoff ability is limited by avalanche injection phenomena.

Optimization of LIGBTs in a dielectric insulated IC-technology using a 'switched anode'

The design of an IGBT is always a compromise between a low on state voltage drop and low switching losses. MOS-controlled emitter shorts are well known as a means to overcome this compromise but previous solutions suffer from parasitic effects and restrictions in the optimization of the high voltage part and the emitter shorting MOSFET. In this paper we propose for the first time an LIGBT where the MOSFET for shorting the p/sup +/-emitter is not merged within the high voltage structure but realized as a separated device integrated on the same chip. It is experimentally shown how with the gate voltage of the bypass MOSFET the composed device can be switched between a MOSFET mode and an IGBT mode, how by proper timing of the control voltage the turn off energy can be reduced to one third, and how it is possible to use the internal p-base/n-substrate diode of the LIGBT.

Turn-On Principles of the MOS-GTO

MOS-GTOs (GTO thyristors which are turned off by the action of a MOS-gate) represent a new generation of controllable thyristors offering considerable advantages in turn-off behavior as compared to conventional GTOs. However, MOS-GTOs generally require one control electrode for turn-on and another control electrode for turn-off, which might be regarded as a disadvantage. It is shown that in MOS-GTOs with a p-channel cathode structure it is possible to turn the thyristor on and off by controlling just one MOS gate electrode. As a triggering current for turn-on, the MOS capacitor charging current is used.

2000-A/1-m Omega power MOSFETs in wafer repair technique

Power MOSFETs with a current capability of up to several thousand amperes and hence an active device area significantly exceeding the typical IC chip size can be realized only if a wafer repair technique is used. A suitable technique has been developed and used to realize circular power MOSFETs with a diameter of 3 cm. The devices are suited to control up to 2000-A drain current and exhibit an on-resistance of R/sub DS(on)/=0.9 m Omega . To contact such a device, a pressure contact system adequate to the high-current value is used. Typical switching times are about 100 ns. Such a large-area MOSFET was used in a MOSFET-GTO (gate turnoff thyristor) cascode circuit to switch anode currents up to 1200 A/1000 V. The total switching time was significantly reduced, and a smaller snubber capacitor could be employed than with the GTO in a conventional circuit. >