D. Takacs

Surface induced latchup in VLSI CMOS circuits

Experimental as well as theoretical results on the latch-up effect in CMOS structures with and without an epitaxial layer are presented. In structures with an epitaxial layer the critical current for latchup firing is two orders of magnitude higher and latchup is essentially surface controlled. The strong surface effect observed is a consequence of the gate influence of surface conduction of the field oxide MOSFETs and on current gains of the bipolar transistors. Latch-up sensitivity can be decreased by increasing p+/p-well and n+/n-well spacing, by decreasing expitaxial layer thickness and by increasing substrate doping. In reducing the lateral dimensions, short-channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.

Comparison of latch-up in p- and n-well CMOS circuits

The latch-up hardness of p- and n-well CMOS concepts is compared for processes with and without epitaxial layer using electrical and laser-scanning measurements as well as theoretical calculations. It is shown that latch-up hardness does not primarily depend on the parasitic bipolar gain products, which are different for the two concepts, but rather on the shunt resistors in the well and in the substrate. This leads to equal latch-up hardness for n- and p-well concepts without epitaxy. With epitaxy latch-up hardness is strongly increased and is in the case of a p-well by a factor of 5 higher compared with the n-well concept. This is due to the enhanced diffusion of Boron from the p+-substrate in the epitaxial layer.

Static and transient latch-up hardness in N-well CMOS with on-chip substrate bias generator

Theoretical considerations and experimental results of the influence of an on-chip substrate bias generator on static and transient latch-up hardness in n-well CMOS are presented. The current drive capability of the VBBgenerator is limited, its internal resistance is operating point dependent. If the VBBgenerator is not capable to sink the static and the time averaged transient substrate currents, localized forward biasing of the substrate takes place, thus triggering latch-up. A special clamp circuit was used for limiting the forward substrate bias below the value capable to trigger the parasitic SCR. Using such clamping techniques the latch-up hardness with on-chip bias generator can significantly be improved during power-up and in normal operation mode.

Improvement of latchup hardness by geometry and technology tuning

A latchup characterization method for CMOS technologies is presented. By separating the role of the parasitic bipolar transistors and the well and substrate shunt efficiencies, the interplay of geometry and technology becomes evident. An optimization of the device latchup hardness is achieved by partitioning the n/sup +/-p/sup +/ spacing with respect to the well. Substrate trigger currents depend on technological features such as substrate doping, well doping, and epilayer thickness. >

N- and P-well optimization for high-speed N-epitaxy CMOS circuits

A double-well n-epi CMOS process was used to investigate the influence of technological parameters relevant to high-speed performance. Dopant concentrations, well depths, channel lengths, and epi-layer thickness have been varied with regard to low propagation delay times measured by three-input NOR/NAND ring oscillators. Parasitic bipolar effects like latchup have been taken into consideration. Ring oscillator circuits designed in general with 3.5-µm design rules and with geometrical gate lengths ≤2 µm exhibited gate delays ≤0.9 ns. The influence of low temperature processing on short-channel and field oxide transistors is discussed.

Reduced n + /p + -spacing with high latchup hardness in self-aligned double well CMOS technology

Latchup in CMOS circuit with an epitaxial layer originates from short channel effects of the parasitic field oxide transistors and from voltage drops on shunt resistances. The short channel behaviour of the field oxide transistors was improved by reducing the p-well depth and modifying the local oxidation step for the well generation. By laser scanning microscope it is shown that for the conventional well latchup firing occurs at the bulges of the well boundary. Using the shallow well the charge compensated region at the well boundary and thereby the latchup sensitive bulges are eliminated. With shallow p-well the shunt resistances are reduced by diminished out-diffusion of the heavily doped n+-substrate and by feasible use of a thinner epi-layer. These measures enable to reduce the critical n+/p+-spacing of adjacent n-and p-channel transistors from 12 µm to 6µm without loosing latchup hardness.

N- and p-well process compatibility in a 1µm-CMOS technology

A 1 µm CMOS concept for 5 V supply-voltage with 22 nm gate oxide and a pure TaSi2gate is presented which allows to realize a n-well- and a p-well-process with widely compatible process flow. Starting in either case from 20 Ωcm epitaxial material on 0.02 Ωcm substrate the process uses equal well depths and identical low well dopant concentrations. Charge carrier mobilities have been found identical in both process concepts. N-channel low-level breakdown voltage is independent of the process concept used. Also independent of the well type the specific junction capacitances inside the well are nearly identical, outside the well typically different. Using ring oscillators with Leff=1.2 µm minimum propagation delays of 120ps for the p-well process and 190ps for the n-well process have been measured.