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Michael T. Fragano

IBM

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Featured researches published by Michael T. Fragano.

custom integrated circuits conference | 2007

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

Larry Wissel; Harold Pilo; Chris LeBlanc; Xiaopeng Wang; Steve Lamphier; Michael T. Fragano

A fixed-configuration custom SRAM macro with a highly-scalable architecture was used as the basis for an ASIC SRAM compiler. The 256 Kb fixed-configuration uses dynamic circuitry (Pito et al., 2004) and other design techniques, and has been demonstrated in silicon to have an access time of 550 ps. The compilable SRAM extends the column mux options, and can be compiled from 2 Kb to 1.1 Mb. Novel circuitry is used for efficient redundancy implementation in both the row and column dimensions.

Archive | 2003

Random access memory having an adaptable latency

Francois Ibrahim Atallah; James Norris Dieffenderfer; Jeffrey Herbert Fischer; Michael T. Fragano; Daniel Geise; Jeffery H. Oppold; Michael R. Ouellette; Neelesh Govindaraya Pai; William Robert Reohr; Joel Abraham Silberman; Thomas Philip Speier

Archive | 2008

Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines

Igor Arsovski; Michael T. Fragano; Robert M. Houle

Archive | 2011

Content addressable memory with concurrent two-dimensional search capability in both row and column directions

Igor Arsovski; Michael T. Fragano; Rahul K. Nadkarni; Reid A. Wistort

Archive | 2003

Method and apparatus for test and repair of marginally functional SRAM cells

Ciaran J. Brennan; Steven M. Eustis; Michael T. Fragano; Michael R. Ouellette; Neelesh Govindaraya Pai; Jeremy Rowland; Kevin M. Tompsett; David J. Wager

Archive | 2000

Self-Test pattern to detect stuck open faults

Michael T. Fragano; Jeffery H. Oppold; Michael R. Ouellette; Jeremy Rowland

Archive | 2008

APPARATUS AND METHOD FOR LOW POWER SENSING IN A MULTI-PORT SRAM USING PRE-DISCHARGED BIT LINES

Igor Arsovski; Michael T. Fragano; Robert M. Houle

Archive | 2008

STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY

Igor Arsovski; Michael T. Fragano; Rahul K. Nadkarni; Reid A. Wisort

Archive | 2010

Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines

Igor Arsovski; Michael T. Fragano; Robert M. Houle

custom integrated circuits conference | 2004

BIST controlled variable sense amp timing for 90nm embedded SRAM

Ciaran J. Brennan; Steven M. Eustis; John R. Goss; A. Humphrey; Michael R. Ouellette; Jeremy Rowland; Michael T. Fragano

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Igor Arsovski

IBM

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Michael R. Ouellette

IBM

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Robert M. Houle

IBM

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Jeremy Rowland

IBM

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Steven M. Eustis

IBM

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Ciaran J. Brennan

IBM

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Harold Pilo

IBM

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Jeffery H. Oppold

IBM

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Neelesh Govindaraya Pai

IBM

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Rahul K. Nadkarni

IBM

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