Michael T. Fragano

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

A fixed-configuration custom SRAM macro with a highly-scalable architecture was used as the basis for an ASIC SRAM compiler. The 256 Kb fixed-configuration uses dynamic circuitry (Pito et al., 2004) and other design techniques, and has been demonstrated in silicon to have an access time of 550 ps. The compilable SRAM extends the column mux options, and can be compiled from 2 Kb to 1.1 Mb. Novel circuitry is used for efficient redundancy implementation in both the row and column dimensions.