Harold Pilo

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-power CMOS Technology. The 62-mm2 die features read-assist and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms. Hardware measurements demonstrate the fail-count improvements achieved by integrating these techniques. The decrease in fail-count provides a 100-mV improvement of VDDMIN during the read operation. Write operations are also improved, especially with weak NFET cell transistors. The circuit techniques have been replicated on a 72-Mb stand-alone standard SRAM product where the area overhead from the additional circuits is approximately 4%. The 32-Mb SRAM has also been successfully migrated to other yield-learning SRAMs in 45-nm bulk and SOI technologies with minimum circuit changes

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology [1]. Figure 14.1.1 shows the 0.154μm2 bitcell (BC). A 2× size reduction from the previous 45nm design [2] is enabled by an equal 2× reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDDMIN operation is enabled by three assist features. Stability is improved by a bitline (BL) regulation scheme. Enhancements to the write path include an increase of 40% of BL boost voltage. Finally, a BC-tracking delay circuit improves both performance and yield across the process space.

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management

A 450 ps access-time 512 Kb SRAM macro is fabricated in a 45 nm SOI technology. The macro is adapted for use as the principal growable embedded-SRAM block in a 45 nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 58% reduction in read power consumption under constant voltage and frequency compared to the previous generation macro. Also described is a single-device dynamic-leakage-suppression scheme that reduces total leakage power consumption by 37% with no wake-up-cycle requirements.

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

A 64Mb SRAM is fabricated in a 22nm high-performance SOI technology [1]. The ever-increasing integration needs of complex SoC are driving the reduction of SRAM leakage power and increase in memory density. While the area and leakage power benefits of eDRAM continue to be leveraged in applications with large contiguous memory blocks [2], SRAM leakage remains a significant portion of the total SoC power. This work describes an SRAM that is optimized for leakage and performance as top priorities over density. The SRAM features a new bitcell (BC) implemented with a fine-granularity power-gating (FGPG) technique to reduce BC leakage by 37%. FGPG improves leakage reduction by 2× compared to bank-based power-gating (PG) techniques [3-4]. Periphery leakage is also reduced by 40% from the previous design [5] with a low-energy power-supply-partition design that leverages higher Vt devices operating at a higher supply voltage. This scheme alone provides an 8% improvement in performance with a small compromise to the AC power.

A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process

A 300 MHz, 1 Mb SRAM with 5.4 ns access in 3.3 V, 0.5 /spl mu/m CMOS uses self-timed and self-resetting circuits. A dual-clock, flow-through read protocol optimizes data window control and a 750 ps setup-and-hold window for all input signals is achieved through floorplanning, receiver design and localized input-signal registering. The SRAM interfaces with high-speed transceiver logic (HSTL) levels through high-speed, noise-tolerant receivers. Programmable impedance output drivers for HSTL interfaces match transmission line impedance to within 10% tolerances over process, voltage and temperature variations.

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

This paper describes an 8 Mb SRAM test chip that has been designed and fabricated in a 45 nm Silicon-On-Insulator (SOI) CMOS technology. The test chip comprises of sixteen 512 kb instances and is designed for use as the principal compilable one-port embedded-SRAM block in a 45 nm ASIC library. Challenges associated with SRAM cell design in SOI are overcome and resulted in a cell size of 0.315 mum2 . The paper introduces two circuit techniques that address the AC and DC power consumption issues facing todays embedded-SRAMs. The first technique addresses AC power dissipation by utilizing a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 68% improvement in read power under constant voltage and frequency compared to the previous generation macro . The second technique addresses the DC power consumption by introducing a single-device, header based dynamic leakage suppression scheme that reduces total macro leakage power by 38% with no wake-up cycle requirements.

A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

This paper describes a 36Mb SRAM with an internal random cycle of 0.9ns and is capable of driving and receiving data at 1.1Gb/s/pin on input and output pins simultaneously. The 115mm/sup 2/ die is fabricated in a 0.13 /spl mu/m process. High-VT array devices are used to reduce array sub-threshold leakage by 22/spl times/. The SRAM features include an improved architecture that segments the 36Mb array into six equal 6Mb sextants. Each sextant supports 1/6th of the 36b I/O width. All sextants of the array are equally timed to reduce the fastest-to-slowest access skew from the previous architecture. Separate input and output pins provide concurrent read and write operations for two random addresses per cycle. The cycle-time is achieved using the improved architecture and a self-timed read to write (STRW) protocol. The STRW protocol improves cycle time by over 20%.

Bitline contacts in high density SRAMs: design for testability and stressability

Process scaling and the need for smaller SRAM cells challenges process technologies to make millions of robust and reliable bitline contacts on a single chip. Another challenge is to identify marginal, resistive and unreliable bitline contacts given the inherent electrical characteristics of the SRAM cell. This paper describes two design techniques that improve the screenability and stressability of bitline contacts in high-density SRAMs. These techniques are developed to overcome the lack of detectability of resistive bitline contacts in SRAM cells.

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

A fixed-configuration custom SRAM macro with a highly-scalable architecture was used as the basis for an ASIC SRAM compiler. The 256 Kb fixed-configuration uses dynamic circuitry (Pito et al., 2004) and other design techniques, and has been demonstrated in silicon to have an access time of 550 ps. The compilable SRAM extends the column mux options, and can be compiled from 2 Kb to 1.1 Mb. Novel circuitry is used for efficient redundancy implementation in both the row and column dimensions.