Rahul K. Nadkarni

An ASIC-embedded content addressable memory with power-saving and design for test features

As the available circuit counts of standard-cell ASICs continue to increase, the issues of power dissipation and testability become increasingly important. In response to this trend, the embedded content addressable memory (CAM) described herein was designed with an emphasis on reducing active power dissipation and on improving the in-system testability via built-in self-test (BIST). At the same time, the CAM macro has been designed with flexibility in mind. Application examples will highlight this aspect of the macro. This CAM has been designed and manufactured in a 0.18 /spl mu/m photolithography process with copper metallization. Results of hardware observations from a test chip confirm functionality in silicon.

Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories

This paper describes a novel test and repair methodology for an embedded content-addressable memory (CAM) design. Exhaustive match-line testing is used to ensure correct search operation after manufacturing, while search margin testing is used to provide robust functionality for the life of the product. With CAM being one of the most power-hungry circuits on chip, it is also important to test the effects of CAM-induced power-supply noise. Programmable BIST patterns induce worst-case power-supply noise in the system and then test CAM sensitivity to it. Fails in the CAM are detected by BIST and repaired using row redundancy with word-line and match-line steering. Hardware results stress the importance of this test and repair methodology

Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines

An embedded content addressable memory (eCAM) uses reduced slew-rate match-line sensing and asynchronous search-line switching to decrease power supply noise while achieving high search speed and low power. When compared to a previous state-of-the-art eCAM, the new design reduces 44% of peak power-supply noise while performing 352M searches/second and consuming 260mW. This reduction in noise directly reduces the amount of decoupling capacitance and, with it, overall chip area. This paper also presents built-in self test patterns for testing search margin and susceptibility to power supply noise. The low-noise eCAM macro has been implemented in 90nm 1.2V CMOS process and is fully functional over a voltage range of 0.7V - 2.05V.

Circuit-dependent F MAX , Power and Process optimization to improve product Reliability, Availability and Serviceability

A fully functional PowerPC476FP SoC communication processor with 4MB eDRAM System Cache achieving 2GHz/Core, in a 4 × 2.5DMIPS/Core/MHz configuration is qualified using physics-of-aging models in a 45nm SOI CMOS technology node including a logic and deep-trench (DT) eDRAM optimized semiconductor process. A novel circuit-depend F<;sub>MAX<;/sub>, Power, and Process optimization methodology that resolves technology reliability limitations (including Stress Migration, EM, BTI, HCI, TDDB, Defects, Package) without product burn-in, while delivering a 9.26% improvement per bin in energy-efficiency across 16 bins and up to 43.9% reduction in failure rate compare to equivalent circuits without the novel optimization methodology is described. Measured results show functional operation with a voltage range of 0.75V to 1.125V, a temperature range of -40C to 125C, speed of 1.8+ GHz at 0.96V, 110C and 90-100% yield performance, for a product lifetime specification of 88KPOH & 2750 ON/OFF cycles. These results demonstrate the highest reliability-aware functional performance reported to date with a 45nm nominal process at 0.9V for a 32-bit Quad-Core communication processor with asymmetric and scalable architecture while achieving the highest reported enterprise-level energy efficiency compare to Quad-Core communication processors in the same class. The technical contributions in this work enables a growing industry trend towards multi-radio ultra-compact stackable base stations designed to drastically reduce the entry price level per base station, enhance scalability and up-gradeability, significantly lower power consumption and enhance flexibility.