Michael Thomas Vaden

IBM POWER6 microarchitecture

This paper describes the implementation of the IBM POWER6™ microprocessor, a two-way simultaneous multithreaded (SMT) dual-core chip whose key features include binary compatibility with IBM POWER5™ microprocessor-based systems; increased functional capabilities, such as decimal floating-point and vector multimedia extensions; significant reliability, availability, and serviceability enhancements; and robust scalability with up to 64 physical processors. Based on a new industry-leading high-frequency core architecture with enhanced SMT and driven by a high-throughput symmetric multiprocessing (SMP) cache and memory subsystem, the POWER6 chip achieves a significant performance boost compared with its predecessor, the POWER5 chip. Key extensions to the coherence protocol enable POWER6 microprocessor-based systems to achieve better SMP scalability while enabling reductions in system packaging complexity and cost.

Resolution of data and control-flow dependencies in the PowerPC 601

he combination of superscalar instruction execution, with out-of-order execution, and speculative branch prediction enables microprocessors like the PowerPC 601’-3 to achieve high performance. However extensive use of such optimizing techniques makes it difficult to maintain the appearance of sequential execution, an important aspect of the PowerPC programming model. There are two main issues associated with maintaining a sequential programming model: resolution of control-flow dependencies and resolution of data dependencies. (For an introductory discussion of control-flow and data dependencies, see the Two types of dependencies box on page 23.) In resolving control-flow dependencies, the PowerPC programming model requires all exceptions to be precise. This means that no instructions after the shift .in control flow (on the not-taken path) affect the machine state (see Definitions box on page 24) and that all instructions before the shift in control flow are completely executed. The shift in control flow is immediate; that is, there are no branch delay slots! Resolution of data dependencies involves ensuring that when an instruction updates the state all subsequent instructions use the new state and instructions before that instruction use the old state. Another responsibility of data dependency resolution is to ensure that, from the programmer’s point of view, each instruction completes before the next instruction starts. Some architectures require the programmer to insert a nondependent operation between one instruction and another instruction that uses its result^.^ The Terence Potter