Michel Depas

New insights in the relation between electron trap generation and the statistical properties of oxide breakdown

In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q/sub BD/ for ultrathin oxides.

Soft breakdown of ultra-thin gate oxide layers

The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.

A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides

A consistent model for the intrinsic time dependent dielectric breakdown (TDDB) of thin oxides is introduced. This model links the existing anode hole injection and the electron trap generation models together and describes wearout as a hole induced generation of electron traps. Breakdown is defined as conduction via these traps from one interface to the other. Implementing the model in a simulator, the oxide thickness dependence of the Weibull slope of the Q/sub BD/-distribution is predicted, and, using the unique relationship between hole fluence and generated electron trap density, the decrease of the critical hole fluence with oxide thickness is explained.

Determination of tunnelling parameters in ultra-thin oxide layer poly-Si/SiO2/Si structures

Abstract In this work the electron tunnelling in device grade ultra-thin 3–6 nm n + poly-Si/SiO 2 /n-Si structures has been analysed. The well known analytic expression for the Fowler-Nordheim tunnelling current was adapted to include the case of direct tunnelling of electrons, which becomes important for oxide layers thinner than 4.5 nm. For these ultra-thin oxide MOS structures it is necessary to take the band bending in the Si substrate and in the poly-Si layer into account to determine the oxide electrical field strength and to derive the tunnelling parameters of the measured current-voltage characteristic. A method is explained to derive the tunnel barrier height φ s and the effective mass of the tunnelling electron m ox from the experimental tunnel current characteristics. It is shown that both the direct tunnelling and the Fowler-Nordheim tunnelling current can be quantitatively explained by a WKB approximation using m ox as the single fitting parameter.

Definition of dielectric breakdown for ultra thin (<2 nm) gate oxides

The different stages of wear-out of an ultra thin 1.7 nm SiO2 during a time dependent dielectric breakdown test of a poly-Si gate metal-oxide-silicon capacitor structure are discussed. For these ultra thin gate oxides, dielectric breakdown already occurs in the direct tunnelling regime. It is shown that the initial continuous increase of the direct tunnel current during constant voltage stress is followed by a complex fluctuation mode. This is defined as the dielectric breakdown of these ultra thin (<2 nm) gate oxide layers and is explained by the formation of a very localised conducting path in the oxide.

Impact of Organic Contamination on Thin Gate Oxide Quality

The impact of organic contamination on the quality of 5-nm-thick gate oxide structures, both before and after gate oxidation, is studied. Sources of organic contamination are chemical surface modification (i.e. hexamethyldisilazane priming), wafer box storage and extended vacuum exposure. Gate oxide integrity is evaluated electrically. The origin and/or nature of the organic contamination is seen to have different effects on the electrical breakdown. Care should be taken when exposing silicon wafers to organic contamination prior to processing. Especially when contamination occurs at the SiO2/polysilicon interface, i.e. prior to a non-oxidizing process step, organics can be extremely deleterious.

Reliability of ultra-thin gate oxide below 3 nm in the direct tunneling regime

Cluster tool furnace technology was used to control the growth of extremely uniform ultra-thin 1.5 nm to 3 nm SiO2 layers on Si. The transition from Fowler-Nordheim tunneling to direct tunneling electron injection for sub-3-nm oxide poly-Si gate metal-oxide-silicon capacitor structures is described and the influence on the oxide reliability is discussed. It is shown that oxide breakdown can still occur at low voltages in the direct tunneling regime under the condition of electron injection from the poly-Si gate. Soft breakdown of these ultra-thin oxide layers, accompanied by the occurrence of complex fluctuations in the direct tunneling current, is demonstrated. Using this as the definition of sub-3-nm oxide breakdown, it is shown for the first time that the time to dielectric breakdown of the sub-3-nm gate oxide in the direct tunneling regime is determined by the electrical field strength in the oxide similarly to the case of the sub-3-nm dielectric breakdown in Fowler-Nordheim tunnel stressing.

Wear-out of ultra-thin gate oxides during high-field electron tunnelling

Ultra-thin (<6 nm) SiO2 wear-out is characterized by time-dependent dielectric breakdown and stress-induced leakage current (SILC) measurements on n+ poly-Si/SiO2/n-Si capacitors, stressed by high-field tunnel injection of electrons from the Si substrate. A drastic increase of the charge to breakdown (QBD) and a strong decrease of the SILC are observed for thinner oxide layers and lower tunnel current densities. This is explained by the corresponding reduction of the hot-electron energy during stressing. With the decrease in gate oxide thickness from 6 nm to 3 nm, a transition from Fowler-Nordheim to direct electron tunnelling is observed in the current-voltage characteristics of the capacitors. It is demonstrated that no significant wear-out occurs in a 3.5 nm oxide layer for direct tunnelling of electrons from the Si substrate.

Breakdown and defect generation in ultrathin gate oxide

In this work the dielectric reliability of thermally grown ultrathin 3 nm SiO2 layers in poly‐Si/SiO2/Si structures is examined. This is compared with a study of the defect generation in the 3 nm gate oxide during tunnel injection of electrons. In these ultrathin SiO2 layers, direct tunneling of electrons becomes very important. An increase of the direct tunnel and Fowler–Nordheim tunnel current during high‐field stressing was observed and is explained by the creation of a positive charge in the oxide associated with slow interface traps. It is demonstrated that a higher current instability corresponds with a lower charge to breakdown value (QBD) of the oxide. From these results we conclude that the creation of slow interface traps is an important precursor effect for the 3 nm gate oxide breakdown.In this work the dielectric reliability of thermally grown ultrathin 3 nm SiO2 layers in poly‐Si/SiO2/Si structures is examined. This is compared with a study of the defect generation in the 3 nm gate oxide during tunnel injection of electrons. In these ultrathin SiO2 layers, direct tunneling of electrons becomes very important. An increase of the direct tunnel and Fowler–Nordheim tunnel current during high‐field stressing was observed and is explained by the creation of a positive charge in the oxide associated with slow interface traps. It is demonstrated that a higher current instability corresponds with a lower charge to breakdown value (QBD) of the oxide. From these results we conclude that the creation of slow interface traps is an important precursor effect for the 3 nm gate oxide breakdown.

A QUANTITATIVE-ANALYSIS OF CAPACITANCE PEAKS IN THE IMPEDANCE OF AL/SIOX/P-SI TUNNEL-DIODES.

An analytic model for the impedance properties of minority-carrier type MIS tunnel diodes is proposed. These devices can display properties different from those of the conventional MIS capacitor if the insulating layer is sufficiently thin. A simple small-signal equivalent circuit is presented that gives a clear explanation for the frequency-dependent peak occurring in the C-V characteristic. It is shown that the dynamical response of the inversion layer is the cause of this nonequilibrium behaviour. Experimental support for the proposed equivalent circuit is given by the measured capacitance of Al/SiOx/p-Si diodes with tunnel oxides grown by rapid thermal oxidation (RTO). The capacitance peak is studied as a function of frequency and oxide layer thickness between 2 and 3 nm. A good agreement between the experimental and simulated results is found for diodes which received a post-oxidation anneal in H2.