Dipankar Pramanik

Lithography-driven layout of logic cells for 65-nm node

The ITRS roadmap for the 65nm technology node, targets poly gate lengths of 65nm and poly pitches between 140-180nm. In addition, contact overlaps and spacing to diffusion contacts will need to be scaled down. It is very likely that the poly layer will be printed using 193nm high NA steppers and Strong Phase Shift Technologies. Attempts to capture the effect of RET on layout by adding more constraints to the desing rules make it difficult to lay out cells using manual tools and can also lead to sub optimal designs. In this paper we describe a methodology that couples automatic cell generation with Phase shifter insertion and image simulation to allow the design space to be explored more fully.

Process Induced Layout Variability for Sub 90nm Technologies

For 65nm and beyond process technologies, identical transistors within a die can show large variations in on-current characteristics for different layouts. The proximity to the transistor of edges associated with different mask levels contribute to variability. Lithography proximity effects are dominant but other physical phenomena encountered with various process steps such as ion scattering, transient enhanced diffusion (TED) and mechanical strain engineering contribute to the variability. These effects can be modeled with TCAD. The results can be incorporated into the current SPICE models to enable designers to do more accurate simulations of the circuit on actual silicon

A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology

For the 65 nm technology node and beyond, new manufacturability problems are arising that strongly impact device and circuit behavior. Among these problems, line-edge and line-width roughness (LER and LWR) are of particular interest as dominant issues affecting parametric yield. In this paper, we investigate LWR effects by applying latest generation, full 3D TCAD technology including lithography simulation. In addition, our results answer open questions concerning the applicability of 2D slicing approximations vis a vis a 3D modeling effort. While LWR has been investigated by TCAD before, our methodology includes a full 3D process simulation (including lithography) without simplifications to generate the final transistor structures

Optimizing manufacturability for the 65-nm process node

The 65nm technology node will require a more detailed assessment of the tradeoffs between performance, manufacturability and cost than any previous generation of technology. Circuits fabricated at the 65nm technology node need to use Strong Phase shifting techniques such as Full-Phase and Model based OPC in order to guarantee printability of critical layers, such as the poly layer. We presents a methodology whereby layouts are genrated base don a preliminary set of design rules for 65nm and the process latitude determined using image simulation software. Mask costs were also estiamted base donfigure counts of the required masks. Tradeoffs between mask costs, manufacturibility and density were made by small changes to the design rules. The simultaneous use of tools that integrate the design creation process with mask generation allows far better optimization than current methodology where physical design is separated from the downstream data preparation and processing.

Assessing technology options for 65-nm logic circuits

The 2001 ITRS roadmap identified the need for tight coupling of design technology with manufacturing technology in order to ensure the successful production of circuits fabricated at the 65nm technology node. The design creation process for 65nm needs to efficiently explore the interaction between device, cell design and manufacturability. Using fast simulation tools for device and lithography simulation and an automated tool for standard cell generation, various process and cell architectural options were investigated. The average and standard deviation of line width had to be matched to the type of application because of the direct relationship between leakage current and performance. Best process latitude for poly line widths is achieved with Full Phase technology. It is shown that by matching design rules to the Full Phase capabilities and using automated layout tools, manufacturabilty could be optizmed without hurting density or performance.