Robert Lugg

Tolerance-based OPC and solution to MRC-constrained OPC

Model based optical proximity correction (MB-OPC) has been widely used in advanced lithography process today. However controlling the edge placement error (EPE) and critical dimension (CD) has become harder as the k1 process factor decreases and design complexity increases. Especially, for high-NA lithography using strong off-axis illumination (OAI), ringing effects on 2D layout makes CD control difficult. In addition, mask rule check (MRC) limits also prevent good OPC convergence where two segment edges are corrected towards each other to form a correction-conflicting scenario because traditional OPC only consider the impact of the current edge when calculating the edge movement. A more sophisticated OPC algorithm that considers the interaction between segments is necessary to find a solution that is both MRC and convergence compliant. This paper first analyzes the phenomenon of MRC-constrained OPC. Then two multiple segment correction techniques for tolerance-based OPC and MRC-constrained OPC are discussed. These correction techniques can be applied to selected areas with different lithographic specifications. The feasibility of these techniques is demonstrated by quantifying the EPE convergence through iterations and by comparing the simulated contour results.

Enriching design intent for optimal OPC and RET

In typical rule- or model-based optical proximity correction (OPC) the goal is to align the silicon layout edges as closely as possible to the corresponding edges in the design layout. OPC precision requirements are approaching 1nm or less at the 0.1mm process node. While state-of-the-art OPC tools are capable of operating at this accuracy, such tight requirements increase computational cycle time, output file size, and photomask fabrication cost. Accuracy requirements on different features in the design may vary widely, and regions that do not need the highest accuracy can be exploited to reduce OPC complexity. For example, transistor gate dimensions require tighter dimensional control than interconnect features on the polysilicon layer. Furthermore gate features typically occupy less area than interconnect. When relaxed OPC accuracy requirements are applied to the interconnect features, but not the gate features, the overall complexity of the polysilicon mask pattern can be significantly reduced without losing accuracy where it counts.

Model based optical proximity correction runtime saving with multisegment solver

In modern photolithography, model based optical proximity correction (MBOPC) has evolved from a nice-to-have feature to a must-have feature and has been widely adopted to improve the process throughput. The purpose of MBOPC is to adjust the designed pattern on the photomask to introduce mask perturbations such that the layout printed on the wafer is as close as possible to the drawn layout. In regular MBOPC process, the polygons are dissected into segments and corrections are conducted segment by segment. While it is relatively easy and straightforward to find the optimal segment size for most one-dimensional features, it is hard for many two-dimensional features, especially line-end areas. By solving a few segments around line-end areas together, multisegment solver (MSS) showed a good contour match. However, this method is expensive on model calculation, as there is more than one segment size to be optimized and a large number of searching iterations is needed, which makes its runtime sensitive to the n...

An Effective Distributed Architecture for OPC & RET Applications

The computational power needed to generate mask layouts for OPC and resolution enhancement techniques increases exponentially with process node. Rapidly growing design complexity is compounded with the more aggressive methods now required for smaller feature sizes. Layers once considered non-critical now routinely receive correction. While some improvement in code efficiency can be expected, algorithms are maturing to the point where improvements will likely not keep pace with the computational need. To maintain required processing cycle times massively parallel processing methods must be employed. In this paper we discuss loosely-coupled distributed computing architectures applied to OPC/RET layout synthesis. The degree to which an application is scalable depends on how well the problem can be divided into independent sets of data. Furthermore, data must also be partitioned into reasonably sized blocks so that memory requirements per processor can be bounded. Communication overhead, I/O overhead and serial processeses all degrade scalability, and may increase overall storage requirements. In this paper we analyze behavior of distributed processing architectures with large numbers of processors, and we present performance data on an existing massively parallel system.

A new methodology for quantifying OPC recipe accuracy

An integrated methodology for developing recipes for optical proximity correction (OPC) is demonstrated. A complete implementation of software programs for generating the OPC corrections, determining mask and layout errors and automatically displaying contours of the worst violations has been accomplished. Integration of these elements facilitates recipe development by quantifying the effect of recipe changes on the overall critical dimension (CD) control. In this paper, a 65nm alternating aperture phase shift test mask is used for illustration of the method. The concept of a recipe comparison matrix is introduced to quantify the effect of recipe changes on across-chip metrics.

An economic analysis for optimal distributed computing resources for mask synthesis and tape-out in production environment

With the exponential increase in output database size due to the aggressive optical proximity correction (OPC) and resolution enhancement technique (RET) required for deep sub-wavelength process nodes, the CPU time required for mask tape-out continues to increase significantly. For integrated device manufacturers (IDMs), this can impact the time-to-market for their products where even a few days delay could have a huge commercial impact and loss of market window opportunity. For foundries, a shorter turnaround time provides a competitive advantage in their demanding market, too slow could mean customers looking elsewhere for these services; while a fast turnaround may even command a higher price. With FAB turnaround of a mature, plain-vanilla CMOS process of around 20-30 days, a delay of several days in mask tapeout would contribute a significant fraction to the total time to deliver prototypes. Unlike silicon processing, masks tape-out time can be decreased by simply purchasing extra computing resources and software licenses. Mask tape-out groups are taking advantage of the ever-decreasing hardware cost and increasing power of commodity processors. The significant distributability inherent in some commercial Mask Synthesis software can be leveraged to address this critical business issue. Different implementations have different fractions of the code that cannot be parallelized and this affects the efficiency with which it scales, as is described by Amdahl’s law. Very few are efficient enough to allow the effective use of 1000’s of processors, enabling run times to drop from days to only minutes. What follows is a cost aware methodology to quantify the scalability of this class of software, and thus act as a guide to estimating the optimal investment in terms of hardware and software licenses.

Improvement in process window aware OPC

In this paper, we present some important improvements on our process window aware OPC (PWA-OPC). First, a CDbased process window checking is developed to find all pinching and bridging errors; Secondly, a rank ordering method is constructed to do process window correction; Finally, PWA-OPC can be applied to selected areas with different specifications for different feature types. In addition, the improved PWA-OPC recipe is constructed as sequence of independent modules, so it is easy for users to modify its algorithm and build original IPs.

Kernel Count Reduction in Model Based Optical Proximity Correction Process Models

As the leading-edge photolithography is approaching rapidly closer to the theoretical optical resolution limit, model based optical proximity correction (MBOPC) has evolved from a nice-to-have feature to a must-have feature. The purpose of MBOPC is to adjust the designed pattern on the photomask to introduce mask perturbations such that the layout printed on the wafer is as close as possible to the drawn layout. Before MBOPC is performed across a full chip, a process model is calibrated based upon manufacturing process data measured from scanning electron microscope (SEM) pictures of test patterns. The process model is usually composed of two components, signal intensity and threshold, and the intersections of these two components determine the layout contours that will be printed on wafer. It is found that the accuracy of the process model is improved as more kernels are used to represent the model. However, pattern correction runtime is proportional to the number of kernels used for the model, thereby introducing a constraint to incorporate least number of kernels in the process model. In this study, a novel method of computing the signal change in the MBOPC process is proposed, which is used to maintain the correction accuracy and reduce the MBOPC runtime.

Fracture friendly optical proximity correction

Optical Proximity Correction (OPC) improves image fidelity by adding and subtracting small enhancement shapes from the original pattern data. Although the presence of these small shapes improves the final wafer image quality, it causes an increase in total figure count, longer fracture processing time, and the introduction of sliver figures. These undesirable artifacts can have a negative impact on the mask write time and mask image quality. In this paper we outline alternative OPC treatments which reduce the additional figures produced, and make the layout configurations friendlier to the subsequent mask fabrication phase. These include the alignment of neighboring small shapes during the OPC operation, and the preservation of jog alignment during the biasing phase. Illustrations of example pattern data, and improvement results in terms of figure counts are described.

AF Fixer : New incremental OPC method for optimizing Assist Feature

Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AFs print more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present, mask manufacturers must downsize AFs below 30nm to solve this problem. This is challenging and increases mask cost. We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in terms of DOF after OPC. We have devised an effective algorithm that removes printing AFs. It can not only search for the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF printing problems economically and accurately.