Michelly de Souza

Threshold voltage in junctionless nanowire transistors

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the dependence on JNT width, height and doping concentration. The quantum confinement has also been taken into consideration in the model formulation. The model is validated using experimental results of nMOS and pMOS JNTs, and three-dimensional TCAD simulations where the nanowire width and height, doping concentration, gate oxide thickness and temperature have been varied. The gate oxide capacitance is also addressed aiming to adequately calculate the capacitance in non-planar devices. The temperature influence on the threshold voltage of JNTs is also analyzed. The presented model shows excellent agreement with both experimental and simulated data, adequately describing the JNT threshold voltage.

An explicit multi-exponential model for semiconductor junctions with series and shunt resistances

An alternative explicit multi-exponential model is proposed to describe multiple, arbitrary ideality factor, conduction mechanisms in semiconductor junctions with parasitic series and shunt resistances. This Lambert function based model allows the terminal current to be expressed as an explicit analytical function of the applied terminal voltage, in contrast to the implicit-type conventional multi-exponential model. As a result this model inherently offers a higher computational efficiency than conventional models, making it better suited for repetitive simulation and parameter extraction applications. Its explicit nature also allows direct analytic differentiation and integration. The model’s applicability has been assessed by parameter extraction and subsequent playback using synthetic and experimental diode forward I–V characteristics.

Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors

The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, the maximum transconductance, the subthreshold slope, the drain-induced barrier lowering (DIBL), and the ION/IOFF ratio are the key parameters under analysis. It has been shown that the negative back bias can reduce the short-channel effects occurrence, improving the ION/IOFF ratio and DIBL.

The zero temperature coefficient in junctionless nanowire transistors

This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows that ZTC may occur in JNTs depending mainly on the series resistance of the devices and its dependence on the temperature. Experimental results of drain current, threshold voltage, and series resistance are presented for both long and short channel n and p-type devices.

Analysis of the leakage current in junctionless nanowire transistors

This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the temperature, device dimensions, and doping concentration have been studied. The results of inversion-mode devices of similar dimensions are also presented for comparison purpose.

Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations

Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (Cgg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (ND), fin width (Wfin) and fin height (Hfin).

Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors

This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode.

Parameter Extraction in Quadratic Exponential Junction Model with Series Resistance using Global Lateral Fitting

A global lateral fitting procedure is proposed to extract the parameters of quadratic double exponential junction models in the presence of parasitic series resistance. Error analysis of the extracted parameters values within a large representative family of synthetic data indicate excellent match between the extracted values and a wide range of the original given model parameters. The procedure was also tested on real data to extract the model parameters of an experimental Silicon PIN diode measured at cryogenic temperature.

Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes short-channel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results.

Drain current model for junctionless nanowire transistors

Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results.