Renan Trevisoli

Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors

The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, the maximum transconductance, the subthreshold slope, the drain-induced barrier lowering (DIBL), and the ION/IOFF ratio are the key parameters under analysis. It has been shown that the negative back bias can reduce the short-channel effects occurrence, improving the ION/IOFF ratio and DIBL.

The zero temperature coefficient in junctionless nanowire transistors

This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows that ZTC may occur in JNTs depending mainly on the series resistance of the devices and its dependence on the temperature. Experimental results of drain current, threshold voltage, and series resistance are presented for both long and short channel n and p-type devices.

Analysis of the leakage current in junctionless nanowire transistors

This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the temperature, device dimensions, and doping concentration have been studied. The results of inversion-mode devices of similar dimensions are also presented for comparison purpose.

Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes short-channel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results.

Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias

This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.

A New Method for Series Resistance Extraction of Nanometer MOSFETs

This paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic curve. The method is based on the Y-function curve, such that the series resistance is obtained through the curve of the total resistance as a function of the inverse of the Y-function. It includes both first- and second-order mobility degradation factors. To validate the proposed method, numerical simulations have been performed for devices of different characteristics. Besides, the method applicability has been demonstrated for experimental silicon nanowires and FinFETs. Apart from that, devices with different channel lengths can be used to estimate the mobility degradation factor influence.

Influence of the crystal orientation on the operation of junctionless nanowire transistors

This work presents, for the first time, an analysis of the influence of the crystal orientation on the electrical performance of Junctionless Nanowire Transistors. Experimental results demonstrate that the device rotation from the standard <;110> to the <;100> direction over a (100) SOI wafer can significantly degrade the performance of the transistors.

Quasi-static analytical model for the dynamic operation of triple-gate junctionless nanowire transistors

This work presents, for the first time, an analytical and explicit model for the intrinsic transcapacitances and transconductances of triple-gate Junctionless Nanowire Transistors. The expressions are derived from a surface potential-based charge model and are validated with 3D TCAD numerical simulations.

A new method for junctionless transistors parameters extraction

This work proposes a new method for the extraction of the flatband voltage, effective nanowire width and doping concentration of junctionless nanowire transistors. The accurate extraction of such parameters is essential for the understating of the device behavior and for the prediction of its performance in circuits through analytical models. The method is validated using 3D numerical simulations and has been applied to experimental short-channel devices proving its applicability.

Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors

This work presented an evaluation of self-cascode association of short-channel junctionless nanowire transistors, by means of experimental results, comparing data of this configuration to single transistors. Even though the self-cascode transistors have shown to reduce de drain current and transconductance level with respect to single device, due to their longer effective channel length, this effect becomes pronounced with the widening of the transistor close to the drain (MD), with consequent threshold voltage reduction. Both symmetric and asymmetric self-cascode configurations do not degrade the efficiency of converting current into transconductance (gm/IDS ratio) in relation to single transistor with same length. On the contrary, the increase of width of MD is capable of reducing the output conductance, reaching values smaller than those obtained for longer single transistors, especially at low gate voltages. The combination of these characteristics results in improved performance for the self-cascode configured as common-source amplifier if compared to symmetric self-cascode or individual longer transistors, reaching a voltage gain increase of up to 17 dB at gm/IDS = 15V-1. When used as common-drain amplifiers, the asymmetric self-cascode junctionless transistors has shown to improve the electrical characteristics (voltage gain and input voltage range) in comparison to a short-channel single transistor, whereas had not shown advantages over a longer single device.