Yoshikazu Fujimori

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-/spl mu/m ferroelectric/CMOS.

Development of Low Dielectric Constant Ferroelectric Materials for the Ferroelectric Memory Feild Effect Transistor

In this paper we discuss ferroelectric materials suitable for a metal-ferroelectric-metal- insulator-semiconductor feild effect transistor (MFMIS FET). It is important for a ferroelectric material to have a low dielectric constant to enable the application of sufficient electric field to a ferroelectric layer. Films of Sr 2 Nb 2 O 7 and Sr 2 (Ta 1-x Nb x ) 2 O 7 were prepared by the sol-gel method on Pt/IrO 2 electrodes for an MFMIS FET. The ferroelectricities of Sr 2 (Ta 1-x Nb x ) 2 O 7 films were confirmed to be in the range of x = 0.1-0.3. In the case of x = 0.3, the largest remanent polarization was obtained in the hysteresis loop. The values of the remanent polarization and the coercive field are 0.5 μC/cm 2 and 44kV/cm, respectively. The film has a low dielectric constant (e r = 53). The characteristics of Sr 2 (Ta 1-x Nb x ) 2 O 7 thin films are suitable for MFMIS FET.

FABRICATION TECHNOLOGY OF FERROELECTRIC MEMORIES

Two types of ferroelectric memories have been proposed. One is a 1 transistor and 1 capacitor (1T1C) type and another is an FET (field effect transistor) type. The fabrication technique for fabrication ferroelectric capacitors on polycrystalline Si (poly-Si) was very effective for high density 1T1C ferroelectric memory and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FET with stable properties. MFMIS FET is one type of FET ferroelectric memory which we proposed. To obtain good ferroelectric capacitors on poly-Si, we used Ir based materials as electrodes of the capacitors. By using Ir based electrodes, the characteristics of Pb(Zi,Ti)O3 (PZT) capacitors on poly-Si were equivalent to those on SiO2. Moreover, the PZT capacitors with Ir based electrodes showed dramatic improvement in fatigue and imprint properties.

Application of Sr2Nb2O7 Family Ferroelectric Films for Ferroelectric Memory Field Effect Transistor

The compounds of the Sr2Nb2O7 (SNO) family are suitable for use as ferroelectric materials for ferroelectric memory field effect transistors (FETs), because these substances have a low dielectric constant, low coercive field and high heat-resistance. In this study, we succeeded in preparing Sr2(Ta,Nb)2O7 (STN) capacitors on polycrystalline silicon (poly-Si). From SIMS profiles, no interdiffusion in the STN metal ferroelectric metal insulator semiconductor (MFMIS) structure was confirmed. C–V and ID–VG hysteresis curves which were dependent on ferroelectric polarization were obtained. These capacitors were applied to floating gate type ferroelectric random access memory (FFRAM) cells. The degradation in ferroelectricity of STN capacitors was not observed during FFRAM cell fabrication process. We succeeded in operating FFRAM cells with a lower voltage than that required for PZT and confirmed the drain current difference of 1 or 2 orders at the 30 s after applying write pulses of ±5 V or ±10 V.

Development of (Pb,La)(Zr,Ti)O3 Electro-Optic Thin Film for High-Speed Spatial Light Modulator

A high-speed electro-optic spatial light modulator (EOSLM) was successfully fabricated with (Pb,La)(Zr,Ti)O3 (PLZT) electro-optic thin film. This EOSLM has a longitudinal structure, so a large electro-optic effect is necessary for low driving voltage (<20 V). We have investigated the relationship between the orientation of polycrystalline PLZT and the electro-optic effect; we found that (111)-orientated PLZT has a large electro-optic effect, which shows a more than 0.025 refractive index change and a 183 pm/V electro-optic constant. With this PLZT film, we fabricated a prototype spatial light modulator (SLM) chip, which has 180×180 pixel arrays. The measured optical switching speed of this device was 7 ns, which is the highest switching speed for two-dimensional pixel array devices. Coded random data is clearly demonstrated with the prototype chip.

A Wearable Healthcare System With a 13.7

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

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The feasibility of SiNx films prepared by catalytic chemical vapor deposition (Cat-CVD) at low substrate temperatures was studied for passivation of ferroelectric non-volatile random access memories (FRAMs). First, the influence of exposure to active NH3 gas generated by the heated catalyzer on ferroelectric Pb(Zr0.52Ti0.48)O3 (PZT) capacitors was examined. Second, SiNx films were prepared by Cat-CVD at low substrate temperature, at which the ferroelectricity of PZT is not degraded. The ferroelectric degradation of PZT capacitors due to exposure to active NH3 gas strongly depended on the sample temperature and the ambient. However, no degradation occurred when keeping the sample temperature below 200°C at an ambient of 1.3 Pa by controlling the heat flow from the catalyzer. By adjusting the flow rate ratio of SiH4/NH3, the refractive index of SiNx films measured by ellipsometry was controlled to be 2.0 for various substrate temperatures. The dense SiNx films, which were resistive to oxidation in air exposure, were prepared at 200°C at an ambient of 1.3 Pa. The ferroelectric PZT capacitors were not degraded during SiNx film deposition using the Cat-CVD method. The results appeared to demonstrate the feasibility of application of Cat-CVD films to passivation of ferroelectric devices.

A Noise Tolerant ECG Processor

Sol-gel derived Pb(Zr,Ti)O3 capacitors were prepared by low-pressure annealing and the two-step annealing techniques. Well-saturated D–E hysteresis was obtained at 650°C with low-pressure rapid thermal annealing. The low-pressure first anneal lowered the crystallization temperature of sol-gel-derived Pb(Zr,Ti)O3 thin films. Highly reliable and low-voltage operation Pb(Zr,Ti)O3 capacitors were obtained using a two-step annealing techniques under low-pressure at 550°C.

Preparation of SiNx passivation films for PZT ferroelectric capacitors at low substrate temperatures by catalytic CVD

This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μA including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.

Low-Temperature Crystallization of Sol-Gel-Derived Pb(Zr, Ti)O3 Thin Films

A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops(NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7us and 3us with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr, Ti)O3(PZT) thin films.