Mickael Gros-Jean

In situ electric field simulation in metal/insulator/metal capacitors

The authors report in this letter the effect of interface topography on metal/insulator/metal (MIM) capacitor electrical properties. This analysis was carried out by numerical simulations of the electric field established in a MIM structure with a 45nm thick Ta2O5 film. The metal/insulator interface profiles have been extracted from transmission electron microscopy micrographs of a fully integrated device. This in situ approach allows direct comparison between electrical properties and numerical simulations performed on the same device. Results show that the bottom electrode’s surface roughness induces a large electric field increase at the interface which could explain MIM capacitor’s asymmetrical electrical behavior.

Method to assess the grain crystallographic orientation with a submicronic spatial resolution using Kelvin probe force microscope

In thin polycrystalline copper film, a direct correlation between the grain crystallographic orientation and the work function has been evidenced by comparing Kelvin probe force microscope (KFM) mapping and electron backscattered diffraction analysis performed over the same region. As a result, work function mapping provided by KFM technique can be used to assess the crystallographic properties of thin layers with a spatial resolution better than 100nm.

Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO 2 -RRAM integrated in a 65nm CMOS technology

In this work, a comprehensive investigation of disturb in HfO2-Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at various temperatures. Data are collected and analyzed on a statistical basis. The SET dependence to the RESET conditions is investigated and correlated to the length of the induced depleted gap along the conductive filament. The conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model. It is shown that thicker dielectric oxide and stronger RESET conditions give rise to longer failure times.

Impact of bilayer character on High K gate stack dielectrics breakdown obtained by conductive atomic force microscopy

Abstract The time to breakdown distribution of bilayer gate stack dielectrics is measured at nanometric scale using an atomic force microscope in conduction mode under ultra-high vacuum. The bilayer consists of a SiON interfacial layer and a HfSiON High-K layer. Thanks to the small tip/sample contact area the time to breakdown distribution of the single interfacial layer is measured separately. It is found that the Weibull parameters of the Interfacial layer distribution are the same as those of the high percentile part of the bilayer bimodal distribution. This experimentally confirms the validity of former dielectric breakdown model assumptions. Considering the fields in each layer an accurate evaluation of acceleration factors and voltage scaling of the bimodal distribution are given.

Reliable 3D damascene MIM architecture embedded into Cu interconnect for a Ta 2 O 5 capacitor record density of 17 fF/μm 2

A new simple 3D Damascene architecture requiring only one additional mask is introduced for high-density MIM capacitors. TiN/Ta₂O₅/TiN stack deposited by PEALD has been integrated between Cu interconnect levels to maximize quality factor Q, reaching up to 17 fF/μm² capacitance. High-performance, breakdown voltages over 15 V and good linearity, C₁ = 76 ppm/V and C₂ = 63 ppm/V² at 100 kHz, make this capacitor an unique solution for analog and RF applications embedded in Cu BEOL.

Impact of TaN/Ta copper barrier on full PEALD TiN/Ta2O5/TiN 3D damascene MIM capacitor performance

MIM capacitors are widely integrated for RF and analog applications. A high density full PEALD TiN/Ta2O5/TiN capacitor is integrated among copper interconnect following an innovative 3D damascene architecture. The impact of a TaN/Ta layer, introduced to avoid Cu diffusion, on both TiN electrode properties and integrated MIM stack performance is studied. Unexpected lower current was obtained without the barrier layer. As a result, up to 17 fF/mum2 capacitance densities were achieved with breakdown voltage over 15 V and excellent voltage linearity.

PEALD ZrO2 Films Deposition on TiN and Si Substrates

a STMicroelectronics 850 rue Jean Monnet 38926 Crolles, France. b SIMaP, Grenoble-INP-CNRS-UJF, 1130 rue de la piscine 38402 Saint Martin d’Heres, France. c CMTC, Grenoble-INP, 1260 rue de la piscine 38402 Saint Martin d’Heres, France. d ESRF 6 rue Jules Horowitz 38043 Grenoble, France. e CEA-LETI, Minatec 17 rue des Martyrs 38054 Grenoble, France. f LPCML, Universite Lyon 1 UMR 5620, CNRS, 10 rue Andre-Marie Ampere 69622 Villeurbanne, France.

Planar Bulk + technology using TiN/Hf-based gate stack for low power applications

This work highlights the new bulk⁺ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to T_si= 8 nm) and thin BOX (T_box = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (W_design/L_gate= 90 nm/40 nm) at V_dd = 1.1 V and I_off < 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum² are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.

Atomic Layer Deposition: An Enabling Technology for Microelectronic Device Manufacturing

Atomic layer deposition (ALD) recently emerged as an enabling technology for microelectronic device fabrication. This technique provides the unique capability to deposit ultra thin films with the thickness control, uniformity, step coverage, and electrical/mechanical properties required to support device manufacturing at the 45 nm node and beyond. This paper will review the fundamentals of ALD processing and describe the equipment used. Applications of ALD in the fabrication of advanced gate stacks, on-chip capacitors, and thin film magnetic heads are presented.

Flatband Voltage Tuning of HfSiON-based Gate Stacks: Impact of High Temperature Activation Annealing and LaOx Capping Layers

INTRODUCTION The aggressive scaling of metal-oxide-semiconductor field-effects transistors (MOSFETS) faces the challenge of metal gate (MG) and high-k (HK) dielectric integration to reduce power consumption [1]. Hf-based oxides and silicates, such as HfSiON, are considered as the most promising candidates for next-generation gate dielectrics, owing to their high permittivity, with a sufficiently wide band gap and a good thermal stability [2]. However, the control of the threshold voltage (Vth) for the advanced nFET and pFET devices is challenging [3]. In gate first approach, the incorporation of LaOx capping layer has been reported to provide Vth shift towards the nFET band edge, yielding the necessary decrease of the effective work function (EWF) of the gate [4]. The mechanism of this voltage shift is attributed to La-induced dipoles at the HK/Si interface [5]. For this reason, the location of LaOx capping layer within the gate stack is a key factor for optimizing the transistor Vth. So far, detailed studies of La-capped gate systems have been focused on HfO2/SiO2 stacks. In this work, we have investigated the impact of high temperature thermal annealing and LaOx capping layer on electronic structure and band discontinuity for TiN/LaOx/HfSiON/SiON/Si gate stacks by coupling hard X-ray photoelectron spectroscopy (HAXPES) with synchrotron radiation and capacitance versus voltage (CV) measurements.