R. Pantel

Strain measurements by convergent-beam electron diffraction: The importance of stress relaxation in lamella preparations

Local convergent-beam electron diffraction (CBED) patterns have been acquired on focus ion beam prepared samples in order to determine the strain field generated by a NiSi layer in a n-MOS transistor. A broadening of the high order Laue zone lines in the transmitted disk of CBED patterns is observed when approaching the NiSi∕Si interface. We show that this broadening is mainly due to the atomic plane bending that occurs as a result of the stress relaxation during the preparation of the thin lamella. From the analysis of this relaxation, we are able to determine the initial stress state of the bulk structure. The presented CBED procedure appears to be a promising tool to measure the strain and stress in any layer or structure deposited on a crystalline substrate.

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

A 200 mm 0.35 /spl mu/m silicon-germanium heterojunction bipolar transistor (SiGe HBT) technology involving epitaxially-aligned polysilicon emitters is described. The devices are shown to combine the high speed performances typical for poly-Si emitter SiGe base devices (f/sub max/ up to 70 GHz) and the low 1/f noise properties of monocrystalline emitter structures (noise figure-of-merit KB as low as 7.2/spl times/10/sup -10/ /spl mu/m/sup 2/). Statistical current gain data are used to demonstrate the manufacturability of this innovative SiGe HBT technology.

Chemical 3D tomography of 28nm high K metal gate transistor: STEM XEDS experimental method and results.

A new STEM XEDS tomography technique is proposed thanks to the implementation of multi EDX SDD detectors in analytical TEMs. The technique flow is presented and the first results obtained on a 28nm FDSOI transistor are detailed. The latter are compared with 2D XEDS analysis to demonstrate the interest of the slice extraction in all directions from a large analyzed volume without any 3D overlap effect issues.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17Å/Vdd 1.1V and 29Å/Vdd 1.8V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators as compared to bulk 45nm devices. In addition, for the first time 99.998% 2Mbit 0.374µm2 SRAM cut functionality has been demonstrated. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IPs required in a SOC are demonstrated for LP applications.

A self-aligned vertical HBT for thin SOI SiGeC BiCMOS

We demonstrate a 4-mask HBT module, which enables the integration of three high performance self-aligned SiGeC HBTs into a 0.13/spl mu/m SOI CMOS technology. Static and dynamic transistor characteristics are described and compared with simulation results and bulk device performances.

Evidence of atomic-scale arsenic clustering in highly doped silicon

Low temperature (675 °C) epitaxial in situ doped Si layers (As, 1.5 at. %) were analyzed by atom probe tomography (APT) to study clustering in a highly arsenic-doped silicon layer. The spatial distribution of As atoms in this layer was obtained by APT, and the distance distribution between first nearest neighbors between As atoms was studied. The result shows that the distribution of As atoms is nonhomogeneous, indicating clustering. Those clusters, homogeneously distributed in the volume, are found to be very small (a few atoms) with a high number density and contain more than 60% of the total number of As atoms.

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0.499 mum2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1V.

Two-dimensional quantitative mapping of arsenic in nanometer-scale silicon devices using STEM EELS―EDX spectroscopy

Field emission gun (FEG) nanoprobe scanning electron transmission microscopy (STEM) techniques coupled with energy dispersive X-ray (EDX) and electron energy loss spectroscopy (EELS) are evaluated for the detection of the n-type dopant arsenic, in silicon semiconductor devices with nanometer-scale. Optimization of the experimental procedure, data extraction and the signal-to-noise ratio versus electron dose, show that arsenic detection below 0.1% should be possible. STEM EDX and EELS spectrum profiles have been quantified and compared with secondary ion mass spectrometry (SIMS) analyses which show a good agreement. In addition, the arsenic doping level found inside large and small epitaxial devices have been compared using STEM EDX-EELS profiling. The average doping level is found to be similar but variable interface segregation has been observed. Finally, STEM EDX arsenic mapping acquired in a BiCMOS transistor cross-section shows strong heterogeneities and segregation in the epitaxially grown emitter part.

Field mapping with nanometer-scale resolution for the next generation of electronic devices.

In order to improve the performance of todays nanoscaled semiconductor devices, characterization techniques that can provide information about the position and activity of dopant atoms and the strain fields are essential. Here we demonstrate that by using a modern transmission electron microscope it is possible to apply multiple techniques to advanced materials systems in order to provide information about the structure, fields, and composition with nanometer-scale resolution. Off-axis electron holography has been used to map the active dopant potentials in state-of-the-art semiconductor devices with 1 nm resolution. These dopant maps have been compared to electron energy loss spectroscopy maps that show the positions of the dopant atoms. The strain fields in the devices have been measured by both dark field electron holography and nanobeam electron diffraction.

250-GHz self-aligned Si/SiGeC HBT featuring an all-implanted collector

This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record fT and fmax (>250 GHz)