Simon Jeannot

28nm advanced CMOS resistive RAM solution as embedded non-volatile memory

A back-end integrated Resistive Random Access Memory (ReRAM) (TiN/HfO2/Ti/TiN) in advanced 28nm CMOS process is evaluated. Significant operating margins and high performances identified at device level (read margin, low power set/reset, endurance and retention) are demonstrated to be significantly reduced on larger statistics, i.e. characterized within 1kbit arrays. The High Resistance State (HRS) dispersion, identified as a limiting factor, is modeled through the “tunneling barrier thickness” variation. The optimization through electrical condition tuning is discussed. A global overview of HfO2 material performances is assessed on statistical basis and projection for larger array integration is discussed.

On the Origin of Low-Resistance State Retention Failure in HfO 2 -Based RRAM and Impact of Doping/Alloying

We study in detail the impact of alloying HfO₂ with Al (Hf_{1_x}Al₂xO_2+x) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal stability through material characterization, electrical measurements, and atomistic simulation. Indeed, migration of oxygen atoms inside the dielectric is at the heart of OxRRAM operations. Hence, we performed comprehensive diffusion barrier calculations in HfO₂, Hf_{1_x}Al₂xO_2+x, and Hf_{1_x}TixO₂ relative to the oxygen vacancy (Vo) movement involved in low-resistance state (RON) thermal stability. Calculations are performed at the best level using ab initio techniques. This paper provides an insight on the improved RON stability of our Hf_{1_x}Al₂xO_2+x-based RRAM devices and predicts the degraded retention of Hf_{1_x}TixO₂-based RRAM measured in the literature. Our theoretical calculations link the origin of RON retention failure to the lateral diffusion of oxygen vacancies at the constriction/tip of the conductive filament in HfO₂-based RRAM.

Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO 2 -RRAM integrated in a 65nm CMOS technology

In this work, a comprehensive investigation of disturb in HfO2-Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at various temperatures. Data are collected and analyzed on a statistical basis. The SET dependence to the RESET conditions is investigated and correlated to the length of the induced depleted gap along the conductive filament. The conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model. It is shown that thicker dielectric oxide and stronger RESET conditions give rise to longer failure times.

Modeling of OxRAM variability from low to high resistance state using a stochastic trap assisted tunneling-based resistor network

In this work, a model is proposed to explain the variability of OxRAM devices, both in their high and low resistive states. This model is based on the calculation of a 3D resistance network, using trap assisted tunneling current. The stochastic nature of the resistance is captured by random placement of traps within a specific spatial distribution.

Benefit of Al 2 O 3 /HfO 2 bilayer for BEOL RRAM integration through 16kb memory cut characterization

In this paper, for the first time, the reliability of HfO₂-based RRAM devices integrated in an advanced 28nm CMOS 16kbit demonstrator is presented. The effect of the introduction of a thin Al₂O₃ layer in TiN/Ti/HfO₂/Al₂O₃/TiN is explored to improve the memory performances. Thanks to the in-depth electrical characterization of both HfO₂ and HfO₂/Al₂O₃ stacks at device level and in the 16×1kbit demonstrator the interest of the bilayer is put forward (endurance: 1 decade after 1M cycles and retention: 6 hours at 200°C). Finally, thanks to our 3D model based on calculation of the Conductive Filament resistance using trap assisted tunneling (TAT) the role of Al₂O₃ as tunneling layer is highlighted.

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO2, SiO2, HfO2, Al2O3, or a combination of those. Because the nanodamascene technology involves processing temperatures lower than 300&#-80;C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.

On the impact of the oxide thickness and reset conditions on activation energy of HfO 2 based ReRAM extracted through disturb measurements

In this paper, the failure acceleration behavior of HfO2 based ReRAM under constant voltage and high temperature stresses is studied. We extract the activation energy from disturb measurements in the High Resistance State (HRS) for different dielectrics. Various Reset conditions are studied and correlated to the failure mechanism. Low activation energy is obtained in thin dielectric oxides. Based on the hypothesis that the activation energy is linked to the number of oxygen vacancies (i.e. residual conductive filament) in the oxide film, we show that an optimal Reset condition (in terms of voltage stop) can reduce the activation energy in thin HfO2. On the other hand, the activation energy is higher in thick dielectrics films and it is also tunable thanks to the voltage stop of previous Reset operation.

Evaluation of ONO compatibility with high-k metal gate stacks for future embedded flash products

Embedded flash memories having high-k metal gate-based logic devices will require modifications to the flash cells in order to remain economically feasible. One potential integration scheme is to keep the traditional ONO layer as the flash cells inter-gate dielectric and replace its poly-Si control gate with the same high-k metal gate stack used for the logic devices. Preliminary electrical tests show that an HfSiON/TiN/a-Si gate stack does not significantly impact the EOT or leakage properties of the ONO layer. This stack is more robust than the traditional ONO with a poly-Si gate.

HfO x complementary resistive switches

This paper proposes the fabrication, together with morphological and electrical characterizations of complementary resistive switches using a nanodamascene process. Complementary switches electrical performance are coherent with ReRAM fabricated and characterized with the same procedure that showed Ron/Roff ratios of 100. Complemetary operating voltages of V th1,3 = |0.8| V and V th2.4 = |1.1| V are obtained for 88×22 nm2 junction with 6 nm thick HfOx.