Mieke Goethals

EUV lithography with the Alpha Demo Tools: status and challenges

ASML has built and shipped to The College of Nanoscale Science and Engineering of the University at Albany (CNSE) and IMEC two full field step-and-scan exposure tools for extreme ultraviolet lithography. These tools, known as Alpha Demo Tools (ADT), will be used for process development and to set the foundation for the commercialization of this technology. In this paper we will present results from the set-up and integration of both ADT systems, status of resist and reticles for EUV, and the plans for using these tools at the two research centers. We will also present the first resist images from one of the tools at the customer site, and demonstrate 32nm half-pitch dense lines/spaces printing as well as 32nm dense contact hole printing.

Performance of the full field EUV systems

The ASML extreme ultraviolet lithography (EUV) alpha demo tool is a 0.25NA fully functional lithography tool with a field size of 26×33 mm2, enabling process development for sub-40-nm technology. Two exposure tools are installed at customer facilities, and are equipped with a Sn discharge source. In this paper we present data measured at intermediate focus of the Sn source-collector module. We also present performance data from both exposure tools, show the latest results of resist exposures including excellent 32-nm half pitch dense staggered and aligned contact hole images, and present the highlights of the first demonstration of an electrically functional full field device with one of the layers made using EUVL in ASMLs alpha demo tool.

Lithography Options for the 32nm Half Pitch Node and Their Implications on Resist and Material Technology

There still remain three major technological lithography options for high volume manufacturing at the 32nm half pitch node: 193nm immersion lithography with high index materials, enabling NA>1.6; 193nm double patterning and EUV lithography. In this paper the pros and cons of these three options will be discussed. Particular interest will be paid to the consequences of the final choice on the resist technology. High index 193nm immersion lithography also requires high index resist materials, which are under development but still far removed from the target refractive index and absorbance specifications not to mention lithographical performance. For double patterning the pitch may be relaxed, but the resists still need to be able to print very narrow lines and/or trenches. Moreover, it would be preferred for the resists to support pattern or image freezing techniques in order to step away from the litho-etch-litho-etch approach and make double patterning more cost effective. For EUV the resist materials need to meet very aggressive sensitivity specifications. In itself this is possible, but it is difficult to simultaneously maintain performance in terms of resolution and line width roughness. A new parameter (KLUP) for assessing resist performance in terms of these three performance criteria will be introduced.

Predictive modeling of EUV-lithography: the role of mask, optics, and photoresist effects

Extreme ultraviolet (EUV) - lithography at a wavelength around 13.5 nm is considered as the most promising successor of optical projection lithography. This paper reviews simulation models for EUV lithography. Resist model parameters are calibrated with experimental data. The models are applied for the investigation of the impact of mask multilayer defects on the lithographic process.

Latest cluster performance for EUV lithography

Previously, fundamental evaluations of the Extreme Ultra Violet (EUV) lithography process have been conducted using the CLEAN TRACK ACT™ 12 coater/developer with the ASML EUV Alpha Demo Tool (ADT) at imec. In that work, we confirmed the basic process sensitivities for the critical dimension (CD) and defectivity with EUV resists. Ultimate resolution improvements were examined with TBAH and FIRM™ Extreme. Moving forward with this work, the latest inline cluster is evaluated using the ASML NXE:3100 pre-production EUV scanner and the CLEAN TRACK™ LITHIUS Pro™ -EUV coater/developer. The imec standard EUV baseline process has been evaluated for manufacturability of CD uniformity control based on half pitch (HP) 27nm and ultimate resolution studies focusing on HP 22nm. With regards to the progress of the improvement for EUV processing, we confirmed the effectiveness of several novel concepts: FIRM™ Extreme10 showed increase in ultimate resolution and improvement in line width roughness (LWR) and process window; Tokyo Electron LTD. (TEL) smoothing process for roughness reduction showed 17% improvement for line and space (L/S) patterns; and finally the new dispense method reduced patterned wafer defectivity by over 50%.

Further investigation of EUV process sensitivities for wafer track processing

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, its shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

Dry Development of Surface Imaging Resists: a Major Parameter for Process Optimization

Most surface imaging resist processes are based on selective incorporation of silicon during silylation, followed by dry development of the resist. The dry development is an important parameter in the resist processing, because it will influence the resist profile and the sensitivity to residues, and, hence, the process latitude. For the DESIRE process, the silicon diffusion profile will be more steep by applying a so called two step dry development, which will result in a steeper resist profile and less residue. For several dry development schemes, the resist profile and the sensitivity to residue are investigated. The etch selectivities corresponding to the various development processes are measured, since they play a major role in the resulting lithographic performance. Further, the useful silylation window with respect to silicon incorporation and DUV induced crosslinking is determined for each type of development. Finally, the resolution and the process latitudes resulting from the different development processes are compared.

EUV processing investigation on state of the art coater/developer system

In order to further understand the processing sensitivities of the EUV resist process, TEL and imec have continued their collaborative efforts. For this work, TEL has delivered and installed the state of the art, CLEAN TRACK™ LITHIUS Pro™ -EUV coater/developer to the newly expanded imec 300mm cleanroom in Leuven, Belgium. The exposures detailed in this investigation were performed off-line to the ASML EUV Alpha Demo Tool (ADT) as well as on the inline ADT cluster with CLEAN TRACK™ ACT™ 12 coater/developer. As EUV feature sizes are reduced, is it apparent that there is a need for more precise processing control, as can be demonstrated in the LITHIUS Pro™ -EUV. In previous work from this collaboration1, initial investigations from the ACT™ 12 work showed reasonable results; however, certainly hardware and processing improvements are necessary for manufacturing quality processing performance. This work continues the investigation into CDU and defectivity performance, as well as improvements to the process with novel techniques such as advanced defect reduction (ADR), pattern collapse mitigation with FIRM™Extreme and resolution improvement with tetrabutylammoniumhydroxide (TBAH).