Geert Vandenberghe

Split and design guidelines for double patterning

Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.

Application challenges with double patterning technology (DPT) beyond 45 nm

Double patterning technology (DPT) is a promising technique that bridges the anticipated technology gap from the use of 193nm immersion to EUV for the half-pitch device node beyond 45nm. The intended mask pattern is formed by two independent patterning steps. Using DPT, there is no optical imaging correlation between the two separate patterning steps except for the impact from mask overlay. In each of the single exposure step, we can relax the dense design pattern pitches by decomposing them into two half-dense ones. This allows a higher k1 imaging factor for each patterning step. With combined patterns, we can achieve overall k1 factor that exceeds the conventional Rayleigh resolution limit. This paper addresses DPT application challenges with respect to both mask error factor (MEF) and 2D patterning. In our simulations using DPT with relaxed feature pitch for each exposure step, the MEF for the line/space is fairly manageable for 32nm half-pitch and below. The real challenge for the 32nm half-pitch and below with DPT is how to deal with the printing of small 2D features resulting from the many cutting sites due to feature decomposition. Each split of a dense pattern generates two difficult-to-print line-end type features with dimension less than one-fifth or one-sixth of ArF wavelength. Worse, the proximity environment of the 2D cut features can then become quite complex. How to stitch them correctly back to the original target requires careful attention. Applying target bias can improve the printing performance in general. But using a model-based stitching error correction method seems to be a preferred solution.

Characterization and correction of optical proximity effects in deep‐ultraviolet lithography using behavior modeling

We present the characterization of optical proximity effects and their correction in deep‐UV lithography using an empirically derived model for calculating feature sizes in resist. The model is based on convolution of the mask pattern with a set of kernels determined from measuring the printed test structures in resist. The fit of the model to the measurement data is reviewed. The model is then used for proximity correction using commercially available proximity correction software. Corrections based on this model is effective in restoring resist linearity and in reducing line‐end shortening. It is also more effective in reducing optical proximity effects than corrections based only on aerial image calculations.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Model-based OPC for first-generation 193-nm lithography

The first 193 nm lithography processes using model-based OPC will soon be in production for 0.13 micrometer technology semiconductor manufacturing. However, the relative immaturity of 193 nm resist, etch and reticle processes places considerable strain upon the OPC software to compensate increased non-linearity, proximity bias, corner rounding and line-end pullback. We have evaluated three leading model-based OPC software packages with 193 nm lithography on random logic poly gate designs for the 0.13 micrometer generation. Our analysis has been performed for three different OPC reticle write processes, two leading 193 nm resists and multiple illumination conditions. The results indicate that the maturity of the model-OPC software tools for 193 nm lithography is generally good, although specific improvements are recommended.

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

The use of customized illumination modes is part of the pursuit to stretch the applicability of immersion ArF lithography. Indeed, a specific illumination source shape that is optimized for a particular design leads to enhanced imaging results. Recently, freeform illumination has become available through pixelated DOEs or through FlexRayTM, ASMLs programmable illuminator system, allowing for virtually unconstrained intensity distribution within the source pupil. In this paper, the benefit of freeform over traditional illumination is evaluated, by applying source mask co-optimization (SMO) for an aggressive use case, and wafer-based verification. For a 22 nm node SRAM of 0.099 μm² and 0.078 μm2 bit cell area, the patterning of the full contact and metal layer into a hard mask is demonstrated with the application of SMO and freeform illumination. In this work, both pixelated DOEs and FlexRay are applied. Additionally, the match between the latter two is confirmed on wafer, in terms of CD and process window.

Comparing positive and negative tone development process for printing the metal and contact layers of the 32- and 22-nm nodes

A strong demand exists for techniques that extend application of ArF immersion lithography. Besides techniques such as litho-friendly design, dual exposure/patterning schemes, customized illumination, alternative processing schemes are also viable candidates. One of the most promising alternative flows uses image reversal by means of a negative tone development (NTD) step with a Fujifilm solvent-based developer. Traditionally, contact and trench printing uses a dark-field mask in combination with positive tone resist and positive tone development. With NTD, the same features are printed in positive resist using light-field masks, and consequently with better image contrast. We present an overview of NTD applications, comparing the NTD performance to that of the traditional development. Experimental work is performed at a 1.35 numerical aperture, targeting the contact/metal layers of the 32- and 22-nm nodes. For contact printing, we consider both single- and dual-exposure schemes for regular arrays and 2-D patterns. For trench printing, we study 1-D, line end, and 2-D patterns. We also assess the etch capability and critical dimension uniformity performance of the NTD process. We proves the added value of NTD. It enables us to achieve a broader pitch range and/or smaller litho targets, which makes NTD attractive for the most advanced lithography applications, including double patterning.

The economic impact of EUV lithography on critical process modules

Traditionally, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter exposure wavelengths or higher numerical apertures have allowed optical lithography be on the forefront of dimensional scaling for the semiconductor industry. Unfortunately, the roadmap for lithography is currently at a juncture of a major paradigm shift. EUV Lithography is steadily maturing but not fully ready to be inserted into HVM. Unfortunately, there are no alternative litho candidates on the horizon that can take over from 193nm. As a result, it is important to look into the insertion point of EUV that would be ideal for the industry from an economical perspective. This paper details the benefit observed by such a transition. Furthermore, it looks into such detail with an EUV throughput sensitivity study.

Lithography Options for the 32 nm Half Pitch Node and Beyond

Three major technological lithography options have been reviewed for high volume manufacturing at the 32 nm half pitch node: 193 nm immersion lithography with high index materials, enabling NA > 1.6; 193 nm double patterning and EUV lithography. In this paper the evolution of these three options over 2008 is discussed. The extendibility of these options beyond 32 nm half pitch is important for the final choices to be made. During 2008, the work on high index 193 nm immersion lithography has been stopped due to lack of progress in high index optical material and high index liquid development. Double patterning has made a lot of progress but cost concerns still exist. Preferred are those resists which support pattern or image freezing techniques in order to step away from the complex litho-etch-litho-etch approach and make double patterning more cost effective. For EUV, besides the high power light source, the resist materials need to meet very aggressive sensitivity specifications and need to maintain simultaneously performance in terms of resolution and line width roughness. Furthermore, EUV reticles encounter serious challenges, primarily related to mask defectivity.

Integrated fab process for metal oxide EUV photoresist

Inpria is developing directly patternable, metal oxide hardmasks as robust, high-resolution photoresists for EUV lithography. Targeted formulations have achieved 13nm half-pitch at 35 mJ/cm2 on an ASML’s NXE:3300B scanner. Inpria’s second-generation materials have an absorbance of 20/μm, thereby enabling an equivalent photon shot noise compared to conventional resists at a dose lower by a factor of 4X. These photoresists have ~40:1 etch selectivity into a typical carbon underlayer, so ultrathin 20nm films are possible, mitigating pattern collapse. In addition to lithographic performance, we review progress in parallel advances required to enable the transition from lab to fab for such a metal oxide photoresist. This includes considerations and data related to: solvent compatibility, metals cross-contamination, coat uniformity, stability, outgassing, and rework.