Mieko Matsumura

A New Study on the Degradation Mechanism in Low-Temperature p-Channel Polycrystalline Silicon TFTs Under Dynamic Stress

Pronounced device degradation and temperature dependence of p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) under pulse stress were investigated. This device degradation is due to the trap states produced by repetition between electron injection and hole injection. The analysis of activation energy affirms that the rapid degradation at high temperature is caused by an increase in the number of trapped holes, to which the negative-bias-temperature stress significantly contributes. The degradation is strongly dependent on the duration of hole injection and the location of the hole-injection region. To produce highly reliable TFT circuits, it is thus important to shorten the duration of hole injection and separate the region of hole injection from that of electron injection

Subthreshold properties of TFTs with laser-crystallized laterally grown polysilicon layers

Trap-density analysis of laterally grown polysilicon films formed by continuous-wave laser revealed the main factor that controls the subthreshold property of low-temperature polysilicon thin-film transistors. In the low-current region, traps at the gate oxide/polysilicon interface are charged and the consequent insensitiveness of polysilicon surface potential to gate bias dominates the subthreshold property. In the higher current region, that is, close to the threshold voltage, a transport mechanism in which carriers are scattered at the grain boundaries becomes the dominant factor governing the subthreshold property.

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.

Effects of interface properties in SiC MOSFETs on reliability

Based on the experience with silicon (Si) devices, some characteristics of silicon carbide (SiC) devices are likely to be misunderstood. In this paper, studies on channel mobility, time dependent dielectric breakdown (TDDB), and negative bias temperature instability (NBTI) in 4H-SiC MOSFETs are reviewed. Through the discussions, it is indicated that SiC-based models, such as local band gap modulation, and models for the relationship between defect energy state and SiC band gap are effective to understand the above characteristics.

A Model for Predicting On-Current Degradation Caused by Drain-Avalanche Hot Carriers in Low-Temperature Polysilicon Thin-Film Transistors

A model for predicting on-current degradation caused by drain-avalanche hot carriers in NMOS low-temperature polysilicon thin-film transistors (TFTs) is described. The amount of trapped charge caused by hot-carrier stress was estimated by using a model describing the lightly doped drain region as an imaginary TFT, and it was found that the amount of trapped charge saturates as voltage-stress time passes. Moreover, the on-resistance increase caused by the trapped charge could be expressed as a function of voltage-stress time (t) , stress drain current (Id_str), and stress drain voltage (Vd_str), i.e., DeltaRon = Id_str exp(-beta/ Vd_str) AtB. This function can be used to predict the on-current degradation of TFTs after a long time for various gate lengths, operation voltages, and crystallinities of polysilicon.

Accelerated Negative-Bias Temperature Degradation in Low-Temperature Polycrystalline-Silicon p-Channel TFTs Under Dynamic Stress

The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed in the case of the device degradation under pulse stress. Pronounced degradation occurs not after DAHC stress application (electron injection) but after NBT stress application (hole injection). NBT stress degradation is locally accelerated after DAHC stress application because the effective gate voltage negatively increases due to trapped electrons during DAHC stress. The trap states and positive charges that were generated by this accelerated NBT stress are considered to be the main cause of device degradation under pulse stress.

Properties of SiGe Films Fabricated by Reactive Thermal Chemical Vapor Deposition Using Lamp Heating

The structural and electrical properties of SiGe films deposited by reactive thermal chemical vapor deposition using a lamp heating system with a source gas mixture of GeF4 and Si2H6 were investigated. In the SiGe film depositions with respective GeF4 and Si2H6 flow rates of 0.06 and 3 sccm, the film structure changed from crystalline to amorphous during the film growth. The results of secondary ion mass spectroscopy analysis and high-temperature deposition suggest that the gas phase reactions cause the structural change. To suppress the gas phase reactions, low-pressure depositions are investigated. The SiGe film deposited at a relatively low pressure of 400 Pa shows good crystallinity. The thin-film transistor with this SiGe film also reveals a high p-channel mobility of about 10 cm2V-1s-1.

High-Quality CVD SiO2 Interfacial Layer Prepared by Cyclic Deposition with O2 Plasma Treatment

We have developed a new process, cyclic deposition with O 2 plasma treatment (C-DOP), to obtain a high-quality interfacial layer (IL) that can be applied to low-temperature poly-Si thin-film transistors (TFTs). The C-DOP process uses sequential deposition followed by O 2 plasma treatment. By increasing radio frequency power during O 2 plasma treatment, the SiO 2 film becomes denser, and the density of the C-DOP-formed SiO 2 becomes close to that of thermal oxide. The amounts of residual impurities, such as OH, H, and C, are decreased by the C-DOP process. We applied the C-DOP process to form a thin IL. It is effective in suppressing the flatband voltage shift (ΔV FB ) due to Fowler-Nordheim negative stress when the IL thickness is more than 5 nm. By applying the C-DOP-formed IL to poly-Si TFTs, drain-current degradation due to drain-avalanche hot-carrier stress is successfully suppressed, and the time to 10% reduction of the drain current is prolonged by 1 order of magnitude.

Direct Observation of Dielectric Breakdown at Step-Bunching on 4H-SiC

The mechanism of dielectric breakdown of oxide on step-bunching of 4H-silicon carbide (SiC) was investigated. Comparing the surface morphology obtained before forming metal-oxide-semiconductor (MOS) capacitor and optical emission on the capacitor under electrical stress, it was cleared that current concentrates on step-bunching and it often caused preferential dielectric breakdown. Based on TEM analysis and the observation of time dependence of emission under the stress, a new model was proposed to explain the dielectric breakdown on step-bunching.

Buried PN junction nanopillar solar cell: A novel approach to reduce recombination loss in surface nanostructure

Nanopillar solar cells have recently attracted considerable attention due to their excellent light trapping property. So far, three types of pn junction structures have been studied for nanopillar cells: the planar deep-junction type, the planar shallow-junction type, and the radial junction type. However, they all suffer serious recombination loss in the heavily doped region of the nanopillar. Here we propose a “buried junction” pn junction nanopillar solar cell, in which the emitter is formed not in the nanopillar, but at the surface region of the substrate. Reduction of the recombination loss in the proposed structure is numerically demonstrated. The buried junction approach opens a new possibility to achieve high-efficiency surface nanostructured solar cells.