Takeo Shiba

Performance of poly-Si TFTs fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.

A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-/spl mu/m CMOS ULSIs

An advanced CMOS design, where a raised source/drain and contact windows are formed over the field oxide is realized by using P-doped SiGe and B-doped Si selective epitaxial growth techniques. Excellent short-channel characteristics and reduced parasitic drain junction capacitance were obtained. NMOS and PMOSFETs with an effective channel length of 0.12 /spl mu/m and ultra-shallow junctions with a depth of 25 nm were fabricated. These devices had a low extension resistance of about 370 /spl Omega//sq.

An analytical and experimental investigation of the cutoff frequency f/sub T/ of high-speed bipolar transistors

The effects of vertical and lateral structures on cutoff frequency and breakdown voltage are investigated for high-speed bipolar transistors. The cutoff frequencies are examined in the range from 2.5 to 80 GHz by analysis and from 3 to 20 GHz by experiment. To attain the maximum cutoff frequency, it is predicted that the collector width, the base width, and the collector concentration should be 0.12 mu m, 0.07 mu m, and 1.2*10/sup 16/ cm/sup -3/, respectively, and that in this scaled transistor, breakdown voltages, BV/sub CE0/ and BV/sub C8O/ should be reduced below 3 and 7.7 V respectively. >

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.

12.4: Late-News Paper: Selectively Enlarging Laser Crystallization Technology for High and Uniform Performance Poly-Si TFTs

A novel method for laser-recrystallized poly-Si layer formation is proposed. The pulse-duration-controlled solid-state laser is utilized to enhance the lateral crystal growth, and an excimer- laser-crystallized poly-Si layer is used as a precursor. The validity of the method is confirmed by superior TFT characteristics of high field-effect mobility (n-ch TIT:μ > 460 cm2/Vs, p-ch TFT: μ > 150 cm2/Vs) with low threshold voltage deviation (Vth: 3 σ < 0.25 V).

Effects of the timing of AC stress on device degradation produced by trap states in low-temperature polycrystalline-silicon TFTs

Device degradation under ac stress in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed with the density of trap states, electron-emission time, and electron-trapping time as foci. LTPS TFTs are shown to incur greater deterioration of characteristics under ac stress than silicon-on-insulator TFTs. Characteristics are more rapidly worsened as the falling time (t/sub f/) of gate pulses becomes shorter in the range below 1 ms. In addition, the degradation produced by a given number of pulses increases with the duration of the low level of the gate pulse in the range up to 1 ms. These behaviors are due to the slow emission of trapped electrons. On the other hand, the device degradation is independent of the duration of the high level of the gate pulse because the electrons are trapped quickly (in less than 1 /spl mu/s) once the level on the gate becomes high. The U-shaped distribution of trap-state density within the energy gap largely determines the dependence of the ac stress degradation on t/sub f/, since trapped electrons for which the emission time is longer than t/sub f/ are not emitted within the period of transient variation of gate voltage, and the number of electrons emitted after the gate has gone low increases with decreasing t/sub f/. Severe degradation is induced by ac stress conditions that correspond to electron emission from the trap states close to conduction band when the TFT is turned off.

29 ps ECL circuits using U-groove isolated SICOS technology

A 0.5- mu m SICOS (sidewall base contact structure) technology is discussed. U-groove isolation technology and 0.5- mu m fabrication technology reduce the transistor size to 60 mu m/sup 2/. The use of a reduced-resistance base polysilicon electrode and a shallow epitaxial layer improves the emitter-coupled logic (ECL) gate delay time by 20% and 30%, respectively. A typical gate delay time of 29 ps and a minimum gate delay time of 27 ps at a switching current of 1.2 mA and an emitter size of 0.4 mu m*2.4 mu m were realized. This U-groove isolated SICOS device is suitable for very-high-speed VLSIs.<<ETX>>

In situ phosphorus-doped polysilicon emitter technology for very high-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-/spl mu/m emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed.

Very-high-speed silicon bipolar transistors with in-situ doped polysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B/sub 2/H/sub 6/. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time. >

High-mobility solution-processed organic thin-film transistor array for active-matrix color liquid-crystal displays

Abstract— A solution-processed organic thin-film-transistor array to drive a 5-in.-diagonal liquid-crystal display has been fabricated, where semiconductor films, a gate dielectric film, and passivation films have all been formed using solution processes. A field-effect mobility of 1.6 cm2/V-sec, which is among the highest for solution-processed organic thin-film transistors ever reported, was obtained. This result is due to semiconductor material with large-grain-sized pentacene crystals formed from a solution and adoption of three-layered passivation films that minimize the performance degradation of organic thin-film transistors.