Yoshiaki Toyota

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.

Effects of the timing of AC stress on device degradation produced by trap states in low-temperature polycrystalline-silicon TFTs

Device degradation under ac stress in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed with the density of trap states, electron-emission time, and electron-trapping time as foci. LTPS TFTs are shown to incur greater deterioration of characteristics under ac stress than silicon-on-insulator TFTs. Characteristics are more rapidly worsened as the falling time (t/sub f/) of gate pulses becomes shorter in the range below 1 ms. In addition, the degradation produced by a given number of pulses increases with the duration of the low level of the gate pulse in the range up to 1 ms. These behaviors are due to the slow emission of trapped electrons. On the other hand, the device degradation is independent of the duration of the high level of the gate pulse because the electrons are trapped quickly (in less than 1 /spl mu/s) once the level on the gate becomes high. The U-shaped distribution of trap-state density within the energy gap largely determines the dependence of the ac stress degradation on t/sub f/, since trapped electrons for which the emission time is longer than t/sub f/ are not emitted within the period of transient variation of gate voltage, and the number of electrons emitted after the gate has gone low increases with decreasing t/sub f/. Severe degradation is induced by ac stress conditions that correspond to electron emission from the trap states close to conduction band when the TFT is turned off.

A New Study on the Degradation Mechanism in Low-Temperature p-Channel Polycrystalline Silicon TFTs Under Dynamic Stress

Pronounced device degradation and temperature dependence of p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) under pulse stress were investigated. This device degradation is due to the trap states produced by repetition between electron injection and hole injection. The analysis of activation energy affirms that the rapid degradation at high temperature is caused by an increase in the number of trapped holes, to which the negative-bias-temperature stress significantly contributes. The degradation is strongly dependent on the duration of hole injection and the location of the hole-injection region. To produce highly reliable TFT circuits, it is thus important to shorten the duration of hole injection and separate the region of hole injection from that of electron injection

Novel 3.3-kV advanced trench HiGT with low loss and low dv/dt noise

Novel 3.3-kV trench IGBT with low loss and low dv_AK/dt noise was developed. The structural feature of the IGBTs is deep p-WELL layers separated from trench gates. This structure suppresses excess V_GE overshoot and then reduces recovery dv_AK/dt. Moreover, this effect is enhanced by reducing the resistance of the deep p-WELL layers (R_FP). It was found that, for the first time, the trade-off characteristics between V_CEsat and recovery dv_AK/dt were drastically improved by separating p-WELL layers from trench gates and decreasing R_FP. The recovery dv_AK/dt could be reduced by 79% more than that for the conventional trench IGBT, maintaining a small V_CEsat and E_on equal to the conventional one.

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.

Observation and Analysis of a Non-Uniform Avalanche Phenomenon in 4H-SiC 4°-Off (0001) p-n Diodes Terminated with a Floating-Field Ring

4H-SiC (0001) p-n diodes terminated with a floating-field ring were found to emit light at breakdown in the opposite direction to that of substrate misorientation when the diodes were fabricated by aluminum implantation and dry-oxidation passivation. Two-dimensional simulation revealed that such non-uniform breakdown was mainly attributable to the asymmetric lateral straggling of implanted aluminum acceptors, rather than the anisotropic nature of the impact ionization coefficient.

Accelerated Negative-Bias Temperature Degradation in Low-Temperature Polycrystalline-Silicon p-Channel TFTs Under Dynamic Stress

The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed in the case of the device degradation under pulse stress. Pronounced degradation occurs not after DAHC stress application (electron injection) but after NBT stress application (hole injection). NBT stress degradation is locally accelerated after DAHC stress application because the effective gate voltage negatively increases due to trapped electrons during DAHC stress. The trap states and positive charges that were generated by this accelerated NBT stress are considered to be the main cause of device degradation under pulse stress.

Mechanism of device degradation under AC stress in low-temperature polycrystalline silicon TFTs

Enhanced device degradation of low-temperature polycrystalline thin-film transistors (poly-Si TFTs) under exposure to AC stress has been quantitatively analyzed. Degradation of the device characteristics of a single-drain (SD) TFT is greater under AC stress than under DC stress over an equivalent period. Hot holes are strongly related to this greater severity of degradation. A lightly doped drain (LDD) TFT is less strongly affected, and the effect here is dominated by the effective drain avalanche hot carrier (DAHC) stress, i.e., period of stress with a duty ratio of DAHC-stress application taken into account. Differences between the electric field in the respective channel regions is responsible for the different degradation properties of SD and LDD TFTs. With substantial contribution from hot-hole and hot-electron concentrations near the drain junctions, we find the severe degradation under AC stress in SD TFTs is caused by increased DAHC stress.

P‐6: A Design Robust Against Hot‐carrier Stress for Low‐temperature Poly‐Si TFT LCDs Fabricated using a 450°C Process

Degradation phenomena of low-temperature poly-Si thin film transistors (TFTs) under direct current (DC) and dynamic stress were thoroughly investigated, and a robust design was developed for TFT LCDs fabricated on a 730×920-mm glass substrate using a 450°C process. A system-in display capability having a stress immunity was also demonstrated.

A Highly Efficient 3.3-kV SiC-Si Hybrid Power Module with a Novel SiC JBS Diode and a Si Advanced Trench HiGT

A 3.3-kV SiC-Si hybrid module, composed of a low-forward-voltage (VF) SiC junction-barrier-Schottky (JBS) diode and a low-saturation-voltage VCE(sat) Si trench IGBT was fabricated and demonstrated highly efficient operation.