Miji Lee

Line Edge Roughness of Metal Lines and Time-Dependent Dielectric Breakdown Characteristics of Low-k Interconnect Dielectrics

We present both experimentally and numerically the effect of the line edge roughness (LER) of metal lines on breakdown characteristics of low-k interconnect dielectrics. Experimental results show that the LER-induced metal-to-metal space variation significantly affects the Weibull slope, field acceleration parameter and hence the time-dependent dielectric breakdown (TDDB) reliability lifetime of sub-100 nm metal-to-metal spacing interconnects. For detailed quantitative explanation of the effect, we have developed a Monte Carlo simulation model, calibrated to experimental results, and performed a number of Monte Carlo simulations under various conditions. Both experimental and numerical simulation results support that lithography and dry etch processes affecting LER are of great importance to ensure robust low-k TDDB reliability of aggressively scaled interconnects.

Effective line length of test structure and its effect of area scaling on TDDB characterization in advanced Cu/ULK process

This study focuses on the cause of deviation of Poisson area scaling trend used for IMD-TDDB reliability of Cu/ULK (k=2.55) process. The effects of test structure, such as the serpent-comb and comb-comb structure, on IMD-TDDB reliability are comprehensively investigated with a simple resistance model to illustrate voltage drop and effective length of metal line. Since effective line length of the serpentine-comb decreases with increasing voltage so as to misread lifetime prediction, care must be taken in the selection of test structure and bias condition for advanced BEOL process development with ULK and its reliability qualification.

Contact resistance of solder bump with low cost photosensitive polyimide for high performance SoC

One of technical hurdles in far back-end of line (FBEOL) process is to assure lower solder bump contact resistance (Rc) associated with photosensitive polyimide (PSPI) and under bump metal (UBM) process. Often, higher bump Rc results in low Vcc shift fails in high performance SoC product. With palpable understanding of outgassing behaviors of PSPI and meticulous characterization of degassing phenomena linked to plasma etch with physical vapor deposition (PVD), we successfully achieved <; 10mΩ bump Rc even with a low cost PSPI without an existing PVD refurbishment. From photo process to package reliability, a far back-end process optimization for cost effective bump production will be presented.

Low voltage IMD-TDDB lifetime model for advanced future logic technology nodes

Scaled advanced technologies with its narrow metal line spaces are prone to very wide variation. Therefore, having an accurate IMD-TDDB lifetime projection as the upcoming technologies shrink in dimensions is critical. It was reported previously that the Weibull shape parameter p is improved at low field stress (use condition) compared to higher fields (stress condition) in regard to field dependence model approach (E, a/E model) [1-2]. In this paper, we show that the P of IMD-TDDB improves as stress field or voltage is reduced through simulation by using the space data obtained from in-line SEM measurement This is further verified by the long-term (up to 8 months of package level) IMD-TDDB experimental data from various technology nodes with 80-100nm pitch. For the voltage projection, we also show that power-law shows better fit to the long term data. The study is highly useful for developing and qualifying the technology node beyond 14nm.

Development of thermal neutron SER-resilient high-k/metal gate technology

We report the experimental procedure and data that establishes the correlation between natural boron (B10) concentration and thermal neutron soft error rate (SER) in an advanced 28nm high-k/metal gate (HK/MG) technology node. Thermal neutron induced singe event upsets (SEU) depend on the concentration of B10 in the contact process adopted for boosting SRAM performance. However, as technology rapidly evolves in terms of transistor feature size and overall design complexity, B10 concentration needs to decrease so as to reduce thermal neutron SER risk. Optimization of contact and eSiGe process can provide a technology profile that is robust against thermal and high energy neutron SER.

Effects of front-end-of line process variations and defects on retention failure of flash memory: Charge loss/gain mechanism

Retention fails on flash memory were comprehensively characterized and fault-isolated for the formulation of failure mechanism. Using in-depth TEM and SIMS characterizations based on electrical findings, we found that FEOL process variations such as contact misalignment (spacer encroachment) and defects (ONO instability and stacking fault), result in retention fail of flash memory. In this paper, the failure mechanism of retention fail governed by charge loss/gain in a same cell is explicated and knobs for robust reliability and decent production are proposed from design and process perspectives.

Borderless contact leakage induced standby current failure on sub-0.15 /spl mu/m CMOS device

For the downscaling of CMOS device design rules with high device performance, the reduced active area forces formation of a borderless contact in local interconnects. As the contact area is decreased with downscaling, it induces failure of device electrical characteristics and reliability. The ultra-shallow junction structures used as basic technology for sub-0.15 /spl mu/m CMOS devices and the junction leakage induced by borderless contact leakage at the shallow trench edge are serious problems for CMOS devices with low standby power dissipation. Recently, several borderless contact structures have been reported (Gallagher et al., 1995; Subbanna et al., 1993; Wen-Chau Liu et al., 2000). In this paper, we estimate the electrical characteristics of borderless contact and demonstrate the borderless contact leakage induced standby failure on a sub-0.15 /spl mu/m 6-Tr SRAM device.

Characterization of plate-like Ni-Sn intermetallic compounds in Sn-Ag solder bump

We characterized plate-like Ni-Sn IMCs in the Sn-2.3wt.%Ag solder bump using high-resolution 3D X-ray microscopy and transmission electron microscopy. Two types of plate-like IMCs (type 1 and 2) were observed in the solder bump. The type 1 is composed of NiSn4, Ni3Sn4 IMCs and Ni. Type 2 is only composed of plate-like NiSn3 IMC. The crystal structures of meta-stable NiSn4 and NiSna IMCs are orthorhombic (oC20) and tetragonal (I4/mcm), respectively. A significantly difference is that both type 1 and type 2 had a distribution of Ni and Sn. Ni and Sn are partially segregated (Ni-rich and Sn-rich) on the mixture of plate-like NiSn4 IMC and Ni, while Ni and Sn are uniformly distributed on the plate-like NiSn3 IMC.

Opportunities for further BEOL technology scaling using power-law IMD TDDB model on 10/14nm BEOL process technologies and beyond

In this paper, we investigated the IMD (Inter-metal Dielectric) TDDB model where the BEOL interconnect physical spacing is reduced to less than 10nm as scaling progresses. IMD TDDB experiments were performed on 14 and 10 nm process technologies which uses double patterning technique having various interconnect line spacing ranging from the minimum design rule to wider spacings. The structures were examined for metal to metal (Mx-Mx) and metal to via (Vx-Mx) structures. Experimental results showed that the voltage and field acceleration parameters increased more than the model predicted below the specific spacing region due to more than expected current reduction during lower bias stress. As a result, it was found that the voltage/field acceleration parameters and the TDDB leakage depended upon the stress voltage below the certain physical spacing. This implied that the field-based TDDB model with constant field acceleration factor did not work in the narrow space region, which is about 18nm physically. Our long-term (up to 8 months of package level) TDDB results on 14nm and 10nm minimum Mx-Vx design rule structures and 1000hrs product HTOL data showed that square root E model is conservative. Power-law model was more appropriate enabling the further technology scaling will be detailed in the paper.

Reliability of fine pitch COF: Influence of surface morphology and CuSn intermetallic compound formation

Chip-on-film (COF) reliability with fine Cu metal on the film tape used as inner or outer leads for bonding with Au bump that forms electrical contact in display driver IC (DDI) chip is reported. In COF structure, Cu metal is fabricated by electroplating and its mechanical strength was characterized using bending test. It is found that the reliability of COF relies on the quality of Cu electroplating and interface of bonding joint that was optimized to provide excellent bending test results.