Jongwoo Park

Phase transformation of programmed NiSi electrical fuse: Diffusion, agglomeration and thermal stability

An advanced CMOS technology process reliability qualification especially for the NiSi poly gated electrical fuse (eFuse) consists of electrical characterization, physical analyses and reliability evaluations. In this paper, insights are given on microstructural behaviors of the programmed NiSi poly gated eFuse induced by the high temperature storage (HTS) test. Both ex- and in-situ transmission electron microscopy (TEM) reveal that the improved post-resistance of the programmed eFuse is attributed to the low temperature growth of Ni3Si2 during HTS test at 250°C. In addition, the Ni agglomeration, the propensity of Ni3Si2 formation on the programmed eFuse with and without void appearance on the fuse link, is comprehensively investigated in conjunction with the eFuse reliability.

Electromigration of NiSi poly gated electrical fuse and its resistance behaviors induced by high temperature

Insight is given on improved behaviors of the programmed NiSi polygated electrical fuse (eFuse) during the high temperature storage (HTS) test. By using a noble transmission electron microscopy (TEM) that includes scanning transmission electron microscopy (STEM), energy dispersive x-ray spectrometry (EDS), electron energy loss spectrometry (EELS) and nano-beam electron diffraction (NBED), microstructural behavior and phase transition of NiSi in the fuse link are painstakingly investigated before and after HTS test. It is found that improved post-resistance of eFuse is attributed to the low temperature growth of Ni3Si2 induced by HTS test at 250°C, which is microscopically proven by both ex-situ and in-situ TEM. In fact, Ni agglomeration, in which Ni resides around void formed in the fuse link, plays an important role of this cystallization. As results, the root causes of improved post-resistance of eFuse are qualitatively substantiated with respect to dynamic phase transformation and microstructural change in the fuse link.

Technology scaling on High-K & Metal-Gate FinFET BTI reliability

High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling. Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.

Interfacial Degradation Mechanism of Au/Al and Alloy/Al Bonds Under High Temperature Storage Test: Contamination, Epoxy Molding Compound, Wire and Bonding Strength

In this paper, the effects of Al pad contamination, epoxy molding compound [biphenyl (BP) and ortho-cresol novolac (OCN)] and wire (Au and alloy) on the propensity for the interfacial degradation of wire bond in a quad flap package under high temperature storage (HTS) tests at 125degC, 150degC, and 170degC are meticulously investigated. The interfacial degradation intends to be explicated in regards to change in surface morphology of Au-Al and alloy-Al intermetallic compound (IMC) and bonding strength as a function of HTS test. The combination of atomic force microscope and Auger electron spectrometry reveals that initial bonding strengths from wire pull and ball shear test decrease with increasing the thickness of contamination layer on Al pad, carbon and oxygen, and subsequent surface roughness. Indeed, the plasma exposure on Al pad prior to wire bonding enhances both mechanical bonding strengths up to 10% and 15%. It is found that the failure behaviors at 125degC are dissimilar to 150degC and 170degC. We first report that Sb diffused from the OCN exists at the intermetallics of Au-Al bonds, leading to rapidly deteriorate mechanical integrity. Furthermore, inductively coupled plasma mass spectrometry affirms that the OCN is a resource of Br. Above 150degC, the interdiffusion of Br and Sb from the OCN significantly impacts the integrity of Au-Al bonds. In turn, such physical degradation mechanism governed by Sb and Br can be linearly accelerated. It is also found that in the case of Au-Al bonds, the life time with the BP is much longer than that with the OCN under the given HTS tests due to less content of halogen ions. In contrast, neither Sb nor Br was found from the intermetallic layers of alloy-Al bond encapsulated with the OCN and BP. Thus, alloy-Al bonding strengths are intact even after longer stressing. With an alloy wire having Pd as an impurity, the growth kinetics of IMC fueled by Br and Sb seems to be sluggish, providing better reliability than Au wire. Obviously, lower flame retardants and higher are critical intrinsic material properties that should be taken into account when a new epoxy molding compound is introduced to pursue cost effectiveness without loosing reliability. Finally, upon painstaking work over a wide range of analyses herein, a quality affordable guideline for the selection of wire type associated with epoxy molding compound that can ensure the long-term reliability is presented in order to secure reliable supplyline management as well as package assembler.

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (tbd) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, tbd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter tbd than with DC at a lower frequency. This is attributed to hole trapping into IL as Vg is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer tbd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because Gm degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.

Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices

Radiation-induced Soft Error Rate (SER) of SRAM built in 14nm FinFET on bulk technology was extensively characterized. Two different SRAM cells, high-performance (HP) and high-density (HD), were irradiated with alpha particles, thermal neutrons, and high-energy neutrons. Empirical results reveal excellent SER performance of FinFET compared to the prior technology nodes, drastically reducing SER FIT rate by 5-10X. It is found that HP cell is more sensitive to a single event upset than HD cell design. We will discuss the effects of charge collection efficiency as one of major parameter and present supporting simulation results.

An experimental study on the TSV reliability: Electromigration (EM) and time dependant dielectric breakdown (TDDB)

TSV is the key component in fabricating 3-D ICs which can bring lower power consumption, higher integration density and shorter interconnection length. Very few works on EM and TDDB of TSV have been done. Thus, TSV macros with BEOL and backside metal were designed and tested adventurously with EM and TDDB reliability perspective. For EM, the void, however, was found at Cu/SiN interface between TSV bottom and backside metal not at TSV itself due to unexpectedly strong reliability of TSV. And also the TDDB occurred at IMD not at TSV dielectric oxide layer. As a result, the minimum level of reliability of TSV has been obtained experimentally in silicon data at least although the reliability of TSV itself has not been assessed exactly. The guide lines for making reliability macros and testing conditions are suggested also by further investigation.

Propensity of Copper Dendrite Growth on Subassembly Package Components Used in Quad Flat Package

Cu dendrite growth of quad flat package linked to epoxy molding compound (EMC), leadframe, and leadframe adhesive tape is comprehensively investigated. Cu dendrite grows particularly in the lead pitch smaller than les 130 mum covering with a leadframe tape, and in turn, it results in a resistive short. Such an appearance is attributed to test procedure of the precondition (30degC/60% relative humidity with 260-degC reflow) followed by biased stress test (125degC/1.95 V), which not only allows moisture condensation in the tape and but also provides bias between the leads. The influences of impurity in EMC and adhesive tape on dendrite formation are quantified with SEM-EDX, Auger electron spectrometry (AES), inductively coupled plasma-mass spectrometry (ICP-MS), and ICP-AES. As a result, the usage of nonhalide EMC can provide more reliable margin than that of larger lead spacing against Cu dendrite growth.

Effects of BTI during AHTOL on SRAM V MIN

We present an optimal method to characterize and mitigate SRAM Vmin shift during Accelerated High Temperature Operating Life (AHTOL) stress test while taking PG BTI effect into account. Prior work has reported that changes in SRAM VMIN during AHTOL stress test have a strong dependency on Bias Temperature Instability (BTI) degradation on PD and PU transistors [1, 2]. In this work, we have found that PG transistor BTI at a practical duty cycle can appreciably alter SRAM VMIN shift during AHTOL. We have expanded SRAM VMIN shift model on the basis of PG BTI as well as PD and PU BTIs. Statistical SRAM cell design with Response Surface Methodology (RSM)/Response Optimize (RO), Z-score method, is used to extract Optimal Z-score Ridge (OZR). OZR provides the optimal SRAM VMIN at both T0 and EOL. Our work has shown that BTI vector with PD, PG, and PU BTI components should be placed on the OZR in VT domain to mitigate VMIN shift during AHTOL. The proposed theory has been confirmed with model-hardware correlation of individual disturbance-/writability-limited VMIN degradations. With a consideration of OZR and BTI vector, we can achieve almost zero VMIN shift of SRAM macro during AHTOL in gate-first high-k metal gate 32nm process.

Reliability of Pb-free preplated leadframe under atmosphere and accelerated aging test

Atmospheric corrosion of Pb-free preplated leadframe (PPF) finish, which causes unacceptable appearance due to discoloration, has been meticulously investigated. The discoloration appears particularly on the shoulder, tip, and sidewall of the leadframe, where bare Cu is directly exposed to the given environments. Such Cu exposure is attributed to the forming and trimming process of the PPF. It is found that the geometrical feature of the ragged shear edge on the sidewall of the PPF is dependent on the condition of a cutting tool. There is a porous Ni layer on the Cu substrate. It is also found that the tarnish products consist of cuprous oxide (Cu/sub 2/O) and cuprous sulfide (Cu/sub 2/S). The depth profile reveals a thick Cu oxidation layer over cuprous sulfide, which implies that the integrity of a dual inline package assembled with the PPF is susceptible when exposed to a relatively higher humidity and sulfur-involved environments. To reproduce the atmospheric corrosion, a variety of laboratory aging tests that include the mixed flowing gas (MFG) test was used. Except the MFG test, the laboratory corrosion that yields Cu oxidation only is not identical to the atmospheric corrosion. As results, electronic devices assembled with the PPF must be sealed into a moisture-barrier bag to extend the shelf life during storage, if particularly they are exposed to relatively harsh circumstances, higher humidity in H/sub 2/S atmosphere.