Tae-Young Jeong

Line Edge Roughness of Metal Lines and Time-Dependent Dielectric Breakdown Characteristics of Low-k Interconnect Dielectrics

We present both experimentally and numerically the effect of the line edge roughness (LER) of metal lines on breakdown characteristics of low-k interconnect dielectrics. Experimental results show that the LER-induced metal-to-metal space variation significantly affects the Weibull slope, field acceleration parameter and hence the time-dependent dielectric breakdown (TDDB) reliability lifetime of sub-100 nm metal-to-metal spacing interconnects. For detailed quantitative explanation of the effect, we have developed a Monte Carlo simulation model, calibrated to experimental results, and performed a number of Monte Carlo simulations under various conditions. Both experimental and numerical simulation results support that lithography and dry etch processes affecting LER are of great importance to ensure robust low-k TDDB reliability of aggressively scaled interconnects.

Effective line length of test structure and its effect of area scaling on TDDB characterization in advanced Cu/ULK process

This study focuses on the cause of deviation of Poisson area scaling trend used for IMD-TDDB reliability of Cu/ULK (k=2.55) process. The effects of test structure, such as the serpent-comb and comb-comb structure, on IMD-TDDB reliability are comprehensively investigated with a simple resistance model to illustrate voltage drop and effective length of metal line. Since effective line length of the serpentine-comb decreases with increasing voltage so as to misread lifetime prediction, care must be taken in the selection of test structure and bias condition for advanced BEOL process development with ULK and its reliability qualification.

Effect of Joule Heating on electromigration in dual-damascene copper low-k interconnects

The effect of Joule heating (JH) on electromigration (EM) was investigated using copper low-k interconnects. We found Blacks empirical EM model works at a very wide stress conditions (I = 0.03 mA ∼ 3.5mA), where the temperature rise by JH ranges from 0°C to 240°C. EM modeling parameters were found to be 1.05eV and 1.4 for EM Ea and n, respectively. Extensive failure analysis and FEM simulations were carried out to understand the EM failure mode at various JH conditions and provide guidelines for the usage of JH-assisted EM test method and design-reliability rules.

Low voltage IMD-TDDB lifetime model for advanced future logic technology nodes

Scaled advanced technologies with its narrow metal line spaces are prone to very wide variation. Therefore, having an accurate IMD-TDDB lifetime projection as the upcoming technologies shrink in dimensions is critical. It was reported previously that the Weibull shape parameter p is improved at low field stress (use condition) compared to higher fields (stress condition) in regard to field dependence model approach (E, a/E model) [1-2]. In this paper, we show that the P of IMD-TDDB improves as stress field or voltage is reduced through simulation by using the space data obtained from in-line SEM measurement This is further verified by the long-term (up to 8 months of package level) IMD-TDDB experimental data from various technology nodes with 80-100nm pitch. For the voltage projection, we also show that power-law shows better fit to the long term data. The study is highly useful for developing and qualifying the technology node beyond 14nm.

Opportunities for further BEOL technology scaling using power-law IMD TDDB model on 10/14nm BEOL process technologies and beyond

In this paper, we investigated the IMD (Inter-metal Dielectric) TDDB model where the BEOL interconnect physical spacing is reduced to less than 10nm as scaling progresses. IMD TDDB experiments were performed on 14 and 10 nm process technologies which uses double patterning technique having various interconnect line spacing ranging from the minimum design rule to wider spacings. The structures were examined for metal to metal (Mx-Mx) and metal to via (Vx-Mx) structures. Experimental results showed that the voltage and field acceleration parameters increased more than the model predicted below the specific spacing region due to more than expected current reduction during lower bias stress. As a result, it was found that the voltage/field acceleration parameters and the TDDB leakage depended upon the stress voltage below the certain physical spacing. This implied that the field-based TDDB model with constant field acceleration factor did not work in the narrow space region, which is about 18nm physically. Our long-term (up to 8 months of package level) TDDB results on 14nm and 10nm minimum Mx-Vx design rule structures and 1000hrs product HTOL data showed that square root E model is conservative. Power-law model was more appropriate enabling the further technology scaling will be detailed in the paper.

EM performance upside of short BEOL interconnects in advanced process technologies: Electrical-thermal finite element simulations and silicon verifications

In this paper, thermal characteristics (Joule heating) induced by currents in short metal interconnect lines are studied. Electrical-thermal 3D-Finite Element Method (FEM) simulation is employed to model the property of temperature in short length metal lines and an empirical yet practical current model with metal line length effect is introduced. Consequently, the Irms current gain up to 25% in short length metal was achieved. This is attributed to the heat dissipation at the line end being much more effective in short metal lines compared to long metal lines. The material properties of interconnects for simulation was obtained using 64nm pitch BEOL process. The simulation results were verified with experiment silicon data using metal test structures.

Early failure of short-lead metal line and its EM characterization with Wheatstone bridge test structure in advanced Cu/ULK BEOL process

Early failure of the short-lead metal line EM (Electromigration) is investigated. Applying Wheatstone bridge (WSB) test structure and 3-parameter lognormal distribution enables to reduce sample size and time-to-fail (TTF) variation governed by early fails causing a poor standard deviation, EM lifetime is accurately predicted and improved by ~280×. In particular, EM TTF at lower percentiles can be well represented by 3-parameter lognormal. With respect to physical aspects of void, EM behaviors of the short-lead and long-lead metal line are addressed based on experimental results compared with Monte-Carlo simulations to support the Blechs back-stress effects.

A practical modeling for transient thermal characteristics of multilevel interconnects

In this study, intuitive is given on time-dependent thermal characteristics in multilevel interconnects subjected to carry either DC or pulsed-DC. FEM simulation is employed to model the propensity of temperature profile with respect to the variety of interconnects having different geometrical features in terms of metal width, metal height and distance between metal and Si substrate. Accordingly, a practical model that enables to prognosis temperature increase resulting from current-driven metal interconnects and temperature decrease after current carried along metal line stops is developed. It is found that a proposed model precisely predicts thermal transient arisen from metal interconnect, regardless of geometrical factors of metal dimension and location. In addition, transient thermal behavior of metal interconnects carrying pulsed DC with various frequencies is investigated. A circuit designer is required to adjust the maximum allowable current carried along metal interconnects according to the frequency of pulsed DC as well as geometrical dimensions of metal interconnects. Hence, robustness in circuit design even in the earlier stage of development phase can be accomplished for metal interconnects by suppressing electromigration and rupture caused by thermal transient.

A modified berman model for the prediction of time-dependent dielectric breakdown (TDDB) characteristics of low-k/ULK interconnect dielectrics from dual-voltage ramp dielectric breakdown (DVRDB) test

We present a modified Berman model that relates breakdown voltage distributions, from dual voltage ramp dielectric breakdown (DVRDB) test, to the distribution of time-to-fail (TTF) during constant voltage stress (CVS) conditions, assuming that dielectric failure behavior under a constant voltage stress follows the square-root E-model. The methodology presented in this work demonstrates a fast and very effective way of extracting the voltage acceleration parameter (i.e., electric field dependence) and predicting TTF under CVS TDDB test conditions. Both low-k (k=3D2.7) and ULK(k<2.5) DVRDB and CVS TDDB data of 45nm and 32nm dielectrics are presented, along with the model predictions and Monte-Carlo simulation results.