B. Gunnar Malm

Spin-Torque and Spin-Hall Nano-Oscillators

This paper reviews the state of the art in spin-torque and spin-Hall-effect-driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential.

High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension

Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of ~ 1.2 times 1013 cm-2 in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single- and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.

Decreased low frequency noise by hydrogen passivation of polysilicon emitter bipolar transistors

The effect of hydrogen passivation by forming gas annealing (FGA) on the bipolar junction transistor low frequency noise was investigated. The results demonstrated a reduced 1/f noise component by a factor of five after FGA, which resulted in a reduced corner frequency. An equivalent input noise spectral density (S-IB) dependence on base current (IB) of S-IB similar to I-B(2) and on emitter area (A(E)) of S-IB similar to A(E)(-1) was observed, both before and after FGA. The interpretations of the results were (a) the 1/f noise was due to carrier number fluctuation, (b) the noise sources were homogeneously distributed over the polysilicon/monosilicon emitter interfacial oxide, and

Dependence of the colored frequency noise in spin torque oscillators on current and magnetic field

The nano-scale spin torque oscillator (STO) is a compelling device for on-chip, highly tunable microwave frequency signal generation. Currently, one of the most important challenges for the STO is to increase its longer-time frequency stability by decreasing the 1/f frequency noise, but its high level makes even its measurement impossible using the phase noise mode of spectrum analyzers. Here, we present a custom made time-domain measurement system with 150 MHz measurement bandwidth making possible the investigation of the variation of the 1/f as well as the white frequency noise in a STO over a large set of operating points covering 18–25 GHz. The 1/f level is found to be highly dependent on the oscillation amplitude-frequency non-linearity and the vicinity of unexcited oscillation modes. These findings elucidate the need for a quantitative theoretical treatment of the low-frequency, colored frequency noise in STOs. Based on the results, we suggest that the 1/f frequency noise possibly can be decreased by improving the microstructural quality of the metallic thin films.

Low-frequency noise in high-k LaLuO3/TiN MOSFETs

The implementation of high-k gate stacks has enabled further scaling in CMOS technology. However it is still challenging due to increased number of trap densities appeared at the high-k interface or in the bulk, mobility degradation and enhancement in the level of low-frequency noise [1]. Previously low-frequency noise in devices with PtSi Schottky-barrier source/drain contacts were studied [2]. In this work the low-frequency noise characterization of MOSFETs with high-k LaLuO3 dielectric and TiN gate is presented. The devices were fabricated on an SOI substrate thinned down to 30 nm by sacrificial dry oxidation and HF wet etching. Active areas were patterned through MESA etching. The process was continued with an optional growth of a 5 nm layer of thermal oxide on the wafers. The high-k LaLuO3 dielectric was deposited by MBE (tLaLuO3=6 nm) and the metal TiN gate by sputtering (tTiN=20 nm). This was followed by in-situ deposition of phosphorus doped poly-Si with tpoly=150 nm. For the reference wafer, the high-k deposition was skipped. PtSi Schottky-barrier source/drain with Boron and Arsenic implantation was carried out for pMOSFETs and nMOSFETs respectively. In the next step, RTA at 700°C was performed for dopant segregation at the PtSi/Si interface. The fabrication process was finalized by metallization and FGA (10% H2 in N2 at 400° C for 30 min).

Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts

This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.

Ge-profile design for improved linearity of SiGe double HBTs

The influence of Ge-profile design on SiGe HBT linearity-harmonic distortion has been quantified using finite element physical device simulation. It was demonstrated that proper Ge-profile tailoring allows the linearity to be improved for both low- and high-current operation. High injection heterojunction barrier effects are shown to have a significant influence on the higher order harmonics. The influence of the Ge-profile design on linearity was found to be comparable to the influence from the epitaxial collector doping profile.

Current Gain Degradation in 4H-SiC Power BJTs

SiC BJTs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.

Influence of transient enhanced diffusion of the intrinsic base dopant profile on SiGe HBT DC and HF characteristics

The influence of transient enhanced boron out-diffusion from the intrinsic base, caused by excess silicon interstitials created during the extrinsic base implantation, has been investigated for a non-selective SiGe HBT process. Devices with different designs of the extrinsic base region were fabricated, where some designs allowed part of the epitaxial base to be implanted with a high boron dose, hereby increasing the number of silicon interstitials close to the intrinsic device. These devices showed a marked degradation of DC characteristics and HF performance. 2D-device simulations were used to investigate the sensitivity in DC and HF parameters to vertical base profile changes. Good agreement was obtained between measured and simulated DC and HF characteristics.

Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I: Analytical Model of the MTJ STO

Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STOs characteristics, while enabling system- and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.