Mike Ma

Experimental Hardware Calibrated Compact Models for 50nm n-channel FinFETs

An analytic potential DG model with quantum mechanical and short channel effects is calibrated to experimental n-channel FinFET data. All C-V and I-V curves from L=10 mum to 50 nm are in excellent agreement with a single mobility model. There is evidence suggesting higher than expected currents from very short fins possibly due to strain enhanced transport effects.

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In this paper, for the hybrid orientation technology (HOT), we propose a modified amorphization/templated recrystallization (ATR) process to improve the material quality. The characterization of Si/SiO2 interface properties for complementary metal-oxide-semiconductor (CMOS) devices fabricated on HOT wafers is demonstrated through charge pumping (CP) and low-frequency (1/f) noise measurements simultaneously. For n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs), devices with the increased defect-removal annealing time bring out a significant decrease in the CP current and the 1/f noise. The results indicate that ATR-induced defects are further repaired and consequently achieve a well Si/SiO2 interface. In addition, the driving current improvement is observed in devices with a small dimension utilizing the modified ATR process. For p-type MOSFETs (pMOSFETs), the direct-current characteristic, CP, and 1/f noise results are comparable between both HOT wafers. It means that the modified process would not affect bonded (110) regions and degrade the device performance. Hence, this modified process could be adopted to improve the fabrication of the CMOS on the HOT wafer using the ATR method. Moreover, the physical origins of the 1/f noise is attributed to a fluctuation in the mobility of free carriers for pMOSFETs and a unified model, incorporating both the carrier- number and correlated mobility fluctuations, for nMOSFETs.

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For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

Interface Properties for CMOS Fabricated on Hybrid Orientation Substrate Using Amorphization/Templated Recrystallization (ATR) Method

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for p-channel metal oxide semiconductor devices fabricated on alternative substrate orientations. This letter reports on the experimental observation and density functional theory (DFT) based theoretical prediction of a valence band offset between the (100) and (110) silicon surfaces directly bonded to each other. This constitutes a different type of junction created by the presence of two different surface orientations in close proximity to each other and not by doping or material variations. Experimentally, this band offset was observed as an asymmetry in the forward and reverse current-voltage characteristics of a two terminal device designed to flow a current across the DSB interface. Further, the valence band offset obtained from DFT simulations was used in a conventional device simulator (TAURUS-MEDICI) to simulate the behavior of this struc...

CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

Multiple-gate-MOSFETs (MuGFET) have better short-channel effects (SCE) control than planar MOSFET and MuGFETs are good candidates to replace planar bulk MOSFET for low power applications. A key feature in the MuGFETs is the recess and undercut of the fins in the buried oxide. Undercut improves gate control of the channel at fin and BOx interface, but also undermines the fin stability, and increases susceptibility to gate etch defects. This paper introduces SOI wafers with nitride buried dielectric that eliminates the undercut, while maintaining good gate control of the channel through higher buried insulator dielectric constant.

Theoretical and experimental investigation of valence band offsets for direct silicon bond hybrid orientation technology

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.

Study of Fin Profiles and MuGFETs built on SOI Wafers with a Nitride-Oxide Buried Layer (NOx-BL) as the Buried Insulator Layer

The origin of the large Vt shift observed in planar FDSOI is the creation of negative charge states in the BOX by F implant. F implant is a suitable approach for planar FDSOI SoC integration with single WF metal gate, but NOT for MuGFETs. F implant degrades electron mobility and the degradation is a function of F dose. The hole mobility is unaffected by F implant.

PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. In this work, the integration of shallow-trench-isolation (STI) after amorphization and templated recrystallization (ATR) scheme for converting surface orientation from (110) to (100) was investigated. By optimizing the trade-off between ATR-induced triangular morphology and DSB layer thickness, a 3X holes mobility improvement and 36% drive current gain were achieved for PMOSFETs fabricated on (110) plane using DSB-HOT. In addition, un-loaded ring oscillators fabricated using DSB substrates show a 38% improvement compared with control CMOS on (100) wafers.

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for PMOS devices that are fabricated on alternative substrate orientations. Significantly higher leakage was observed for P+/N diodes if the junction depletion region was located close to the interface between the (110) and (100) Si surfaces. Hydrogen and fluorine passivation of this interface by ion implantation resulted in an order of magnitude improvement in the reverse leakage. In this brief, the experiments that performed using several dose levels of H2, F, and N implants are described. Electrical characterization data for reverse leakage, forward current, and ideality factors are presented in the form of cumulative probability plots, from which it is concluded that H and F passivation by ion implantation consistently provides a significant improvement in junction leakage, as compared to an unimplanted DSB wafer. An increase in the forward resistance was observed due to the implants, as compared to bulk Si (100) control samples.

Amorphization and Templated Recrystallization (ATR) Study for Hybrid Orientation Technology (HOT) using Direct Silicon Bond (DSB) Substrates

This paper reviews MuGFET (multi-gate MOSFET) devices performance under extreme temperature range (5-573 K) and total radiation dose up to 6 Mrad. It is concluded that MuGFET is not only a good platform for CMOS scaling, but also an excellent platform for operation in harsh environments.