Kimmo Koli

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

Direct delta-sigma receiver architecture is introduced for wireless communication systems, such as LTE or WiMax. Architecture is based on direct downconversion, delta-sigma feedback that is up-converted to RF, and N-path filtering technique. Hence, the core receiver functions including channel selection filtering are embedded to a RF ADC with excellent linearity performance. This is achieved by transforming narrow-band filtering partially to RF injecting feedback into the input of the second amplifier stage, hence relieving requirements of the most critical subsequent stages. A 900-MHz direct delta-sigma receiver prototype occupies an active area of 1.2 mm2 in 65-nm CMOS. The receiver for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and delta-sigma modes, respectively, and out-of-band IIP3 up to +4 dBm when the delta-sigma loop is active. The chip consumes 80 mW from a 1.2-V supply.

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

Analysis and Design of N-Path Filter Offset Tuning in a 0.7–2.7-GHz Receiver Front-End

N-path techniques have become a popular candidate alternative to external pre-selection filtering in wireless receivers. Their main attraction lies in enabling tunable on-chip high- Q filters, with straightforward migration from one CMOS node to another. However, parasitic capacitance at the N-path filter input offsets the bandpass response from the desired center frequency in wideband circuits. In this paper, we focus on an LNA-first receiver and show that the offset at the LNA output varies in magnitude depending on LNA and filter load impedance properties. An offset-tuning approach is then evaluated for its effects on receiver gain and noise and to obtain design guidelines. We propose a digitally controllable implementation that preserves front-end gain and linearity, with a small penalty on receiver NF. A programmable 0.7-2.7-GHz front-end in 40-nm CMOS verifies the functionality. At 1.7 GHz, the front-end has a gain of 37 dB, a NF of 5.2 dB, and an out-of-band IIP3 of +1 dBm.

Characteristics of LNA Operation in Direct Delta–Sigma Receivers

This brief analyzes the dual role and operation of the low noise amplifier (LNA) in the recently introduced direct delta-sigma receiver (DDSR). First, the LNA functions as a transconductor in an integrator stage, and in this role, we explore the effects of LNA output impedance on quantization noise shaping by the system. In the second role of a voltage preamplifier, we show how the closed-loop DDSR structure impacts LNA voltage gain and system noise. LNA and system properties are thus intertwined and lead to the need for careful codesign. The reliability of the utilized continuous-time DDSR approximation is verified by simulating a sample receiver model.

A 2.5-GHz Receiver Front-End With Q-Boosted Post-LNA N-Path Filtering in 40-nm CMOS

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of > 0 dBm, while consuming 48 mA from a 1.1-V supply.

N-path g m C filter modeling and analysis for direct delta-sigma receiver

This paper presents the analysis and a model for obtaining the delta-sigma loop filter coefficients of a direct delta-sigma receiver (DDSR). The analysis is done by modeling a key element of the DDSR, the N-path filter, with an s-plane transfer function in the baseband. The s-plane model includes the most important non-idealities, such as switch resistances and the limited output resistances of the RF-stages. The model allows the designer to approximate the key parameters for DDSR and enables the optimization of the DDSR performance. As an example, the coefficients of a third-order DDSR are obtained by examining the s-plane and the corresponding z-plane signal and quantization noise transfer functions. The results are evaluated with circuit level simulations.

A 900MHz direct ΔΣ receiver in 65nm CMOS

A 900 MHz direct-conversion receiver with a ΔΣ feedback loop to RF occupies an active area of 1.2 mm² in 65 nm CMOS. The concept prototype for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and ΔΣ modes, respectively, and out-of-band IIP3 up to ±4 dBm when the ΔΣ loop is active. The chip consumes 80 mW from a 1.2 V supply.

Next-Generation RF Front-End Design Methods for Direct

RF-to-digital conversion is a recent approach to digital-intensive wireless receiver operation. Such converters often employ delta-sigma (ΔΣ) modulation to transcend the traditional divide between receiver RF front-ends and baseband analog-to-digital converters (ADC). Research on the direct delta-sigma receiver (DDSR) architecture is one example of the emergence of next-generation ΔΣ modulators. It embeds a direct conversion receiver front-end as part of a feedback-type ΔΣ modulator structure with an active loop filter, which extends ADC operation to RF and changes the role of the low-noise amplifier (LNA) and mixing stages. RF-to-digital converters thus merge the two formerly separate design domains, requiring a paradigm shift in both RF and ADC design methods. Accordingly, this paper uses the DDSR as an example to bridge the gap between RF and ADC design, by providing a systematic understanding of the role, modeling, and design strategy of the related complete RF front-end. Most importantly, the analysis produces new design equations that link analog RF stage properties to their continuous-time (CT) ΔΣ modulator coefficients, thus providing a useful circuit design tool.

\Delta\Sigma

Emerging digital-intensive receiver architectures require new methods for input matching design. In particular, closed-loop ΔΣ-based receivers inject discrete-time global feedback to the RF low-noise amplifier (LNA) output. When using feedback LNA topologies with local internal feedback, receiver input matching thus no longer depends only on analog LNA characteristics, but also on the transfer function of the full receiver chain. This paper proposes a systematic input matching design method for such receivers. We demonstrate how this method is applied to the recently introduced active direct delta-sigma receiver (DDSR). We also show that global ΔΣ feedback in the DDSR counteracts the effects of the local feedback of the LNA on receiver input impedance, and how this can be used to improve receiver performance. A generic DDSR input impedance model is thus developed to facilitate input matching design. The related design method does not require transistor-level description of the post-LNA blocks, but relies instead only on easily obtainable system-level properties. A design example and measurements of a 0.7-2.7-GHz DDSR in 40-nm CMOS verify a good match between the theoretical and experimental results.

Receivers

This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.