Milind Weling

Gate oxide damage reduction using a protective dielectric layer

Gate oxide damage from charge entering through the top surface of the gate electrode during plasma ashing, ion implantation, and LDD spacer oxide etching was measured using antenna structures. Significant charge damage to the 9.0 nm-thick gate oxide was detected for each of these processes. The damage was reduced by using a protective dielectric layer, in this case a thermally deposited TEOS oxide over the polycide gate electrode before gate definition. The dielectric appears to block charge penetration into the antenna. Damage can be reduced further by increasing the thickness of the dielectric layer; for a sufficiently thick layer (about 150 nm), charge entering through the top surface of the antenna was effectively eliminated.<<ETX>>

Damage to thin gate oxide during lightly doped drain spacer oxide etching

Charge buildup damage to gate oxide during lightly doped drain (LDD) spacer oxide etch was studied by measuring gate leakage of fully processed transistors over thin oxide attached to area‐intensive or edge‐intensive polycide antenna structures over thick oxide. Wafers were etched at the LDD spacer oxide etch step for various overetch times ranging from −7% to +35%. It was found that gate oxide damage from charge buildup depended strongly on spacer overetch time. No charge buildup was detected before endpoint (defined as the time required to completely remove oxide from flat silicon surfaces—the polycide has a cap oxide layer on it, so the gate electrode is not exposed at endpoint), but significant charge buildup occurred through the polycide surface when etching was continued past endpoint. Gate leakage failures for transistors attached to large area‐intensive antennas increased monotonically with overetch time, leading to 100% failure after 20%–30% overetch. This charge buildup damage began to occur eve...

A 0.6 micron triple level metal process for high performance application specific integrated circuits

Abstract This paper describes a 0.6 micron triple level interconnect scheme for ASIC application. This interconnect scheme has been used with 0.6 micron twin well CMOS technology having polycide gates. Excellent planarization of BPSG films was achieved at a low reflow temperature by using TEOS/0 3 -based APCVD BPSG. Sandwich layers of TiW/Al-1%Cu/TiW were used for interconnects. A void-free Inter-Metal-Oxide (IMO) planarization with good device reliability was achieved using a combination of silicon-rich silane-based PECVD oxide, TEOS-based PECVD oxide and SOG etchback process. In order to achieve the maximum packing density, metal 3 is used as a routing layer and has the same pitch as metal 1 and metal 2 layers. It has been demonstrated that the device and the interconnect reliabilities for this metallization scheme are excellent.

Effects of resist strip processing damage on the electrical characteristics of 0.8-um a-Si antifuse circuit elements

Field-programmable ASICs have been implemented using a variety of programmable circuit elements, including SRAM, EPROM, E2PROM, and antifuse cells. Amorphous silicon (a-Si) antifuse cells offer greater packing densities and superior performance compared to cells based on memory elements, and they can be integrated into conventional multi-layer integrated circuits with the addition of several process modules. Despite their advantages, a potential yield issue with a-Si antifuses is that their electrical characteristics can be affected by damage from manufacturing processes. In this study, it is found that the programming voltage is reduced when a solvent-based post-resist strip solution is applied to the bottom electrode layer of TiW. Atomic-force microscopy (AFM) shows that the resist strip solution increases the micro-roughness of TiW films. It is also found that the `off-state leakage current increases when the solution is applied to the a-Si antifuse layer. The amount of the leakage current increase is related to the amount of a-Si loss due to the strip solution.

Improved Planarization for a Sog Etchback Process by Modifying the PECVD Oxide Film

In this study we have shown, for the first time, that Inter-Metal Oxide (IMO) planarization using a spin-on-glass (SOG) etchback process can be significantly improved by changing the composition of the deposited PECVD oxide film. Earlier studies have emphasized the importance of lowering the SOG to PECVD oxide etch selectivity below unity to compensate for micro-loading effects and thereby achieve good planarization. However, we have shown that a range of selectivities could be obtained by merely changing the silicon-richness of the PECVD oxide film. It was observed that for a given etch selectivity, planarization after SOG etchback was better with a silicon-rich oxide than with a stoichiometric oxide and particularly so for tight spacings that are characteristic of sub-micron technologies. We believe that increasing the silicon-richness of the PECVD oxide suppresses the micro-loading effects and consequently enables operation at selectivities closer to unity while maintaining good planarization. This feature has an important advantage of significantly widening the process window for a SOG etchback application.