Subhas Bothra

Control of Plasma Damage to Gate Oxide during High Density Plasma Chemical Vapor Deposition

Gate oxide damage resulting from high density plasma chemical vapor deposition of silicon oxide was investigated using damage sensitive antenna structures with area ratios up to 200,000 :1. Significant damage was detected from an unoptimized oxide deposition process. A 2 4-1 fractional factorial experimental design was used to screen the effect of four parameters : radio frequency power, microwave power, electrostatic chuck potential, and magnetic field. RF power and electrostatic chuck potential made no contribution to oxide degradation. The main factor was microwave power, and further experiments with microwave power ranging from 1500 to 2500 W showed that gate charging damage increased with microwave power, with the extent and distribution of damage depending on the magnetic field shape.

A new failure mechanism by corrosion of tungsten in a tungsten plug process

The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.

Corrosion of tungsten due to plasma charging in a metal plasma etcher

Accelerated corrosion of tungsten in tungsten-plug vias was observed due to charging of certain test structures during metal etch in a plasma etcher. This charge is shown to be a positive charge and is responsible for the accelerated dissolution of tungsten during subsequent wet solvent strip processes. It is shown that this phenomenon can be avoided by passivating the tungsten in a low pH solution, such as dilute nitric acid, and by using an electron beam to discharge the metal structures, prior to immersing the wafers in a polymer strip solvent.

Application of charge based capacitance measurement (CBCM) technique in interconnect process development

The charge based capacitance measurement (CBCM) technique (Chen et al, IEDM p. 69, 1996) was used in order to measure femto-farad level intermetal capacitances between metal lines in different configurations. The results are presented and compared with the calculated numbers using the Rafael simulation program. These structures are used to evaluate the impact of process changes such as the use of low k dielectric on parasitic interconnect capacitance. The parasitic capacitances are determined by using a variety of interconnect structures with varying line width and spacing. Such measurements with low k materials show that the formation of these materials in small narrow spaces may be quite different from that in wide open areas.

Integration of a W-plug in an Al-based metallization scheme for 0.25-μm IC technology

Tight interconnect design rules associated with 0.25 micrometer technology and below introduces a number of challenges in backend integration in the course of developing an appropriate process architecture. In this paper, the effect of the underlying metallization on via electrical performance and the attendant integration issues are discussed. For a Ti/TiN/Al-based metal stack, increasing the TiN cap thickness was found to significantly reduce via resistance. Since high density plasma CVD is commonly used to deposit gap-fill oxide after metal patterning, the effect on via resistance of oxygen plasma exposure of the underlying metal stack was also evaluated. A layer of Ti sandwiched between Al and cap TiN was found to give consistently low via resistance values due to reduction of the interfacial resistance contribution from the via/bottom metal interface. In some cases, where W remained exposed after dry etching of the subsequent metal level, complete corrosion of W was observed during solvent strip, for certain structures. Based on these results, various via integration options for current and future multilevel metal interconnect architecture are considered.

Rapid in-line characterization of plasma-induced damage on a 0.25 /spl mu/m CMOS ASIC technology

An investigation into CMOS gate oxide failures during the process development of an advanced 0.25/spl mu/m CMOS ASIC process is presented. Using a SEM technique called passive voltage contrast (PVC), specific backend process steps contributing to the failures were rapidly identified as titanium deposition and SiN deposition. Both these processes are plasma based processes and the failures were addressed by applying a basic understanding of plasma charging induced damage mechanisms. This case study demonstrates the value of PVC in the rapid in-line characterization of gate oxide integrity, and in facilitating quick-turn isolation and elimination of the sources of damage.