Jeong-Hoon Oh

Novel U-Shape Resistive Random Access Memory Structure for Improving Resistive Switching Characteristics

We firstly propose a novel U-shape resistive cell structure which is the best fit for generating low power resistive random access memory (RRAM) with forming-less process. We find that irregular resistive switching behavior in the initial transition and the characteristics associated with it. Controlling the conducting filament (CF) dimension and deposition orientation of resistive material are expected to reduce the distribution and forming voltage, which enables low power RRAM to be feasible without forming state. Simple fabrication flow and device performances are also evaluated in the aspect of forming-less process. Numerical simulation is performed using random circuit breaker model (RCB) to confirm the proposed structure.

Areal and Structural Effects on Oxide-Based Resistive Random Access Memory Cell for Improving Resistive Switching Characteristics

A new technical improvement in understanding the resistive switching characteristics of unipolar resistive random access memory (RRAM) is investigated. It is possible to minimize reset current (IRESET), set voltage variation, and forming voltage (VFORMING), which results in a wide sensing margin and high density applications by using a conducting filament (CF) minimized structure up to a 10 nm technology node. Its structural advantages enable IRESET to be tuned with excellent manufacturability. Numerical simulation is also performed using a random circuit breaker (RCB) model, showing that the proposed structure elucidates the resistive switching improvement.

Bipolar resistive switching characteristics in Si 3 N 4 -based RRAM with MIS (Metal-Insulator-Silicon) structure

In this paper, bipolar resistive switching was investigated in our fabricated Ti/Si3N4/p+-Si resistive random access memory (RRAM) devices. Heavily doped p-type Si was used instead of a conventional bottom electrode (BE) using metal such as Pt. We found that forming-free process, self-compliance and gradual reset were shown in this device. The operation voltage was with 1.8~3.5 V during set process due to forming-free process. And self-compliance was observed by restriction of parasitic resistance without external current limiter. Finally, multi-level cell (MLC) feasibility was achieved using voltage stop during gradual reset.

Reset Current Reduction with Excellent Filament Controllability by Using Area Minimized and Field Enhanced Unipolar Resistive Random Access Memory Structure

We firstly propose a novel resistive random access memory (RRAM) cell structure, which makes it possible to minimize the switching area and to maximize the electrical field where resistive switching occurs, resulting in the improvement of resistive switching characteristics. With excellent structural advantages, resistive switching characteristics such as reset current and set voltage fluctuation are improved through the enhancement of conductive filament (CF) controllability. A simple fabrication process is delivered and the device performance from the viewpoints of the forming voltage, set voltage, and reset current is investigated. Conducting defect effects are also investigated in comparison with the conventional RRAM cell structure. Numerical simulation is performed using a random circuit breaker (RCB) model to confirm the proposed structure.

Effect of Oxidation Amount on Gradual Switching Behavior in Reset Transition of Al/TiO2-Based Resistive Switching Memory and Its Mechanism for Multilevel Cell Operation

To analyze and explain the gradual reset switching property of the bipolar switching resistive random access memory (RRAM) for multilevel cell (MLC) operation, the effect of the amount of plasma oxidation on the gradual reset switching behavior of the Al/TiO2-based RRAM cell structure is investigated. The device that undergoes plasma oxidation in a shorter time has a better ON/OFF current (ION/IOFF) ratio and shows increased ON current (ION). The device that undergoes long plasma oxidation occasionally shows the step reset switching behavior because of the thick conductive filament formation in the ON state. This is clearly explained by the different conduction mechanisms during the ON state.

Novel Protruded-Shape Unipolar Resistive Random Access Memory Structure for Improving Switching Uniformity through Excellent Conductive Filament Controllability

Resistive random access memory (RRAM) with a new structure which can effectively control switching area and electric field is proposed. It has been verified that the decrease in area of resistive material with the new structure increases electric field of switching area, and that such increased electric field makes initial forming at unipolar switching rather easier, resulting in effective decrease in forming voltage. Also, as the area in switching area is effectively reduced, decrease in reset current and set voltage in a limited area has also been verified. Excellent resistive switching characteristics are possible by decrease of conductive filament (CF) area in our structure. Random circuit breaker (RCB) simulation model which can effectively explain percolation switching similar to unipolar switching verifies such structural effect.

Off-state degradation with ac bias in PMOSFET

Abstract For the first time, the current failure of p-channel MOSFETs used for the sub-wordline driver of state-of-the-art DRAM chips was investigated during off-state switching cycles. With increasing switching speed for the sub-wordline driver, the subthreshold leakage current of p-channel MOSFETs increased, and resulted in serious stand-by current failure. The model proposed in this work suggested that the off-state degradation of p-channel MOSFETs with ac bias will intensify as the dimensions of devices decrease due to both the high electric field and the high operating frequency. The roles of various device parameters- such as gate length, gate-tab width, doping concentration at the source/drain extensions, operating temperature and operating frequency- on the degradation of p-channel MOSFETs were investigated.

Roles of Residual Stress in Dynamic Refresh Failure of a Buried-Recessed-Channel-Array Transistor (B-CAT) in DRAM

We clarify the role of metal gates (e.g., TiN) on the degradation of the state-of-the-art buried-channel-array transistor (B-CAT) in dynamic random access memory (DRAM) chips. Unless the thermal budget during the processing step for integration is well controlled, residual stress caused by grain growth of the metal gate can result in a dynamic refresh failure of B-CAT through the negative shift in threshold voltage (-ΔVth). A hole trapping model is proposed to explain this phenomenon. Uncontrolled grain growth of the metal gate increases the residual stress level on SiO2, and, consequently, it breaks the strained Si-O-Si bonds, which can serve as precursor sites for incoming holes. Residual stress in the three-dimensional transistor architecture, therefore, must be well controlled to improve the reliability of commercial DRAM chips.

Investigation of conduction mechanism in Ti/Si 3 N 4 /p-Si stacked RRAM

The conduction mechanism in Ti/Si3N4/p-Si memory stack is described. In order to analyze the conduction mechanism, we measured the I-V characteristics in voltage sweep mode and conducted I-V curve fitting. And the temperature dependence in Ti/Si3N4/p-Si stacked cell is also investigated because we cannot claim the conduction mechanism just based on the I-V curve fitting. From I-V curve fitting and temperature measurement data, we found that space charge limited conduction (SCLC) model is well fitted in both high resistance state (HRS) and low resistance state (LRS).