Min-Ho Kang

Vertically Integrated Multiple Nanowire Field Effect Transistor

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.

A Vertically Integrated Junctionless Nanowire Transistor

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.

Crystal Quality Effect on Low-Frequency Noise in ZnO TFTs

The effect of ZnO active film quality on the low-frequency noise behavior in ZnO thin-film transistors has been investigated. The film crystalline is varied by differentiating the thickness and adding postannealing. To discriminate the origin of 1/f noise, the gate bias dependence of noise spectra is investigated. It is found that the number fluctuation noise model related with trapping/detrapping by traps near the interface becomes dominant as the crystal quality improves, which is also confirmed by another noise parameter, i.e., α Extracted αapp can also well explain the electrical characteristics.

Thermally Robust Ni Germanide Technology Using Cosputtering of Ni and Pt for High-Performance Nanoscale Ge MOSFETs

Thermally robust Ni germanide (NiGe) using the cosputtering of Ni and Pt on Ge-on-Si substrate is proposed for high-performance nanoscale germanium metal-oxide-semiconductor field-effect transistors (Ge MOSFETs). The rapid thermal process temperature window for the stable sheet resistance of the proposed Ni-Pt cosputtered structures was about 50-100°C wider than that of the pure Ni structure, with neither NiGe agglomeration nor local penetration of Ni atoms into the substrate. In addition, the surface and interfacial morphologies of the Ni-Pt cosputtered structure were much smoother and more continuous than those of a pure Ni structure. The improvement in the thermal stability was attributed to the change of the crystal structure due to the suppression of the diffusion of Ni atoms and the uniform distribution of Pt atoms. Therefore, this proposed Ni-Pt cosputtered structure could be promising for high-mobility Ge-on-Si MOSFET applications.

A high-density and low-cost self-aligned shallow trench isolation NOR flash technology with 0.14/spl mu/m/sup 2/ cell size

We have developed a new cell technology with extremely small cell size of 0.14 /spl mu/m/sup 2/ using 0.12 /spl mu/m process. The self-aligned shallow trench isolation (SA-STI) and self-aligned source (SAS) structure are adopted to minimize the cell size. To scale down the cell gate length and to improve the cell performance, high aspect-ratio floating gate and channel erasing scheme are used. Excellent endurance characteristics, tight threshold voltage distribution and good reliability have been verified in this work.

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor.

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs.

A Novel FinFET With High-Speed and Prolonged Retention for Dynamic Memory

A trigate FinFET with a charge trap gate dielectric is demonstrated for high-speed and long retention memory applications. For a capacitor-less dynamic memory cell, a nitride layer is utilized as a charge storage node and it is directly formed on a silicon channel. In addition, novel gate-stacks allow high-speed and write processes under low voltage WITH remarkably endurable operation of up to 1012 cycles. By virtue of the charge trap operation, stored data is maintained for >104 s at 125°C.

Vertically Integrated Nanowire-Based Unified Memory

A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications.

Low-Frequency Noise Characteristics in SONOS Flash Memory With Vertically Stacked Nanowire FETs

Low-frequency (LF) noise in a vertically stacked nanowire (VS-NW) memory device, which is based on the silicon-oxide-nitride-oxide-silicon (SONOS) configuration is characterized in two different operational modes, an inversion-mode and a junctionless-mode (JM). The LF noise showed 1/f -shape behavior regardless of the operational mode and followed the carrier number fluctuation model. With regard to the device-to-device variation and quality degradation of the LF noise after iterative program/erase operations, the five-story JM SONOS memory showed comparatively high immunity arising from its inherent bulk conduction and no-junction feature. Despite the harsh fabrication condition used to construct five-story VS-NW, even the five-story JM SONOS memory exhibited LF noise characteristics comparable to those of one-story JM SONOS memory. Thus, the five-story JM SONOS memory is attractive due to its high-performance capabilities and good scalability.