Ga-Won Lee

Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-

The behavior of ID random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO2/TaN is experimentally investigated and discussed. The ID-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of ID-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔID/ID) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, ID-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.

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In this paper, thermally stable Ni germanide using a Ni-Pt(1%) alloy and TiN capping layer is proposed for high-performance Ge MOSFETs. The proposed Ni-Pt(1%) alloy structure exhibits low-temperature germanidation with a wide temperature window for rapid thermal processing. Moreover, sheet resistance is stable and the germanide interface shows less agglomeration despite high-temperature postgermanidation anneal up to 550 °C for 30 min. In addition, the surface of the Ni-Pt(1%) alloy structure is smoother than that of a pure Ni structure both before and after the postgermanidation anneal. Only the NiGe phase and no other phases such as PtxGey and NixPt1-xGey can be observed in X-ray diffraction results, but X-ray photoelectron spectroscopy shows that PtGe is formed during the postgermanidation anneal. The larger Pt atomic radius is believed to inhibit the diffusion of Ni into the Si substrate, thereby improving the thermal stability of the NiGe. The higher melting point of PtGe is also believed to improve thermal stability. Therefore, this proposed Ni-Pt(1%) alloy could be promising for high-mobility Ge MOSFET applications.

Dielectric/Metal Gate

In this article, ytterbium (Yb) incorporation into NiGe is proposed to improve the thermal stability of Ni germanide for high-performance Ge metal-oxide-semiconductor field-effect transistors (Ge MOSFETs). The Yb/Ni/TiN structure shows suppression of NiGe agglomeration and better surface morphology than the Ni/TiN structure after a postgermanidation annealing of up to 550°C for 30 min. It is notable that Yb atoms distribute uniformly at the top region of NiGe. NiGe agglomeration was retarded by Yb incorporation, and the thermal stability of NiGe was therefore improved.

Improvement of Thermal Stability of Ni Germanide Using a Ni–Pt(1%) Alloy on Ge-on-Si Substrate for Nanoscale Ge MOSFETs

The effect of ZnO active film quality on the low-frequency noise behavior in ZnO thin-film transistors has been investigated. The film crystalline is varied by differentiating the thickness and adding postannealing. To discriminate the origin of 1/f noise, the gate bias dependence of noise spectra is investigated. It is found that the number fluctuation noise model related with trapping/detrapping by traps near the interface becomes dominant as the crystal quality improves, which is also confirmed by another noise parameter, i.e., α Extracted αapp can also well explain the electrical characteristics.

Ni Germanide Utilizing Ytterbium Interlayer for High-Performance Ge MOSFETs

Thermally robust Ni germanide (NiGe) using the cosputtering of Ni and Pt on Ge-on-Si substrate is proposed for high-performance nanoscale germanium metal-oxide-semiconductor field-effect transistors (Ge MOSFETs). The rapid thermal process temperature window for the stable sheet resistance of the proposed Ni-Pt cosputtered structures was about 50-100°C wider than that of the pure Ni structure, with neither NiGe agglomeration nor local penetration of Ni atoms into the substrate. In addition, the surface and interfacial morphologies of the Ni-Pt cosputtered structure were much smoother and more continuous than those of a pure Ni structure. The improvement in the thermal stability was attributed to the change of the crystal structure due to the suppression of the diffusion of Ni atoms and the uniform distribution of Pt atoms. Therefore, this proposed Ni-Pt cosputtered structure could be promising for high-mobility Ge-on-Si MOSFET applications.

Crystal Quality Effect on Low-Frequency Noise in ZnO TFTs

In this article, incorporating ytterbium into Ni-silicide using an Yb interlayer is proposed to reduce the work function of Ni-silicide for a Ni-silicided Schottky barrier diode. The proposed Ni-silicide exhibited good Schottky barrier diode characteristics owing to the reduced work function of about 0.15−0.38 eV. Even though the ytterbium layer was deposited below nickel, a ternary phase (YbxNi1−x)Si is formed at the top region of the Ni-silicide, which is believed to reduce the work function.

Thermally Robust Ni Germanide Technology Using Cosputtering of Ni and Pt for High-Performance Nanoscale Ge MOSFETs

Semi-transparent, colored organic light-emitting diodes (OLEDs) were demonstrated by comprising a microcavity-embedded structure that uses an organic layer sandwiched between thin metal layers as the cathode. Without bias, the colored OLEDs exhibited various colors depending on the metal/organic/metal cathode configuration, by means of internal interference effects under ambient illumination. By varying the thickness of the organic layer, the transmittance and reflectance of the colored OLEDs could be controlled. The influence of the microcavity cathode on the light-emitting performances of OLEDs, such as the efficiencies and the electroluminescence spectra, was also studied.

Work function variation of nickel silicide using an ytterbium buffer layer for Schottky barrier metal-oxide-semiconductor field-effect transistors

— The effects of gate-bias stress, drain-bias stress, and temperature on the electrical parameters of amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors have been investigated. Results demonstrate that the devices suffer from threshold-voltage instabilities that are recovered at room temperature without any treatments. It is suggested that these instabilities result from the bias field and temperature-assisted charging and discharging phenomenon of preexisting traps at the near-interface and the a-IGZO channel region. The experimental results show that applying a drain-bias stress obviously impacts the instability of a-IGZO TFTs; however, the instability caused by drain bias is not caused by hot-electron generation as in conventional MOSFETs. And the degradation trend is affected by thermally activated carriers at high temperature.

Colored semi-transparent organic light-emitting diodes

In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = −20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

Instability dependent upon bias and temperature stress in amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors

In this paper, electrical analysis was carried out on ZnO thin-film transistors (TFTs) to investigate the effects of the Al2O3 interlayer between the ZnO active-layer and the SiO2 gate insulator. The Al2O3 interlayer was deposited via atomic layer deposition. From the electrical analysis, it was found that the Al2O3 interlayer improves the electrical properties, such as the subthreshold slope and on/off-current ratio. The stability degradation under positive bias stress, however, is severe in TFTs with an Al2O3 interlayer. According to the crystallographic view, the crystal structures in a ZnO film on Al2O3 are prone to align in the (002) direction compared with ZnO on SiO2, and can attract more oxygen ions because of the Zn polar, which degrades the stability of devices.