Dae-Chul Ahn

Vertically Integrated Multiple Nanowire Field Effect Transistor

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.

A Vertically Integrated Junctionless Nanowire Transistor

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.

Physically Transient Memory on a Rapidly Dissoluble Paper for Security Application

We report the transient memory device by means of a water soluble SSG (solid sodium with glycerine) paper. This material has a hydroscopic property hence it can be soluble in water. In terms of physical security of memory devices, prompt abrogation of a memory device which stored a large number of data is crucial when it is stolen because all of things have identified information in the memory device. By utilizing the SSG paper as a substrate, we fabricated a disposable resistive random access memory (RRAM) which has good data retention of longer than 106 seconds and cycling endurance of 300 cycles. This memory device is dissolved within 10 seconds thus it can never be recovered or replicated. By employing direct printing but not lithography technology to aim low cost and disposable applications, the memory capacity tends to be limited less than kilo-bits. However, unlike high memory capacity demand for consumer electronics, the proposed device is targeting for security applications. With this regards, the sub-kilobit memory capacity should find the applications such as one-time usable personal identification, authentication code storage, cryptography key, and smart delivery tag. This aspect is attractive for security and protection system against unauthorized accessibility.

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor.

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs.

Vertically Integrated Nanowire-Based Unified Memory

A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications.

Low-Frequency Noise Characteristics in SONOS Flash Memory With Vertically Stacked Nanowire FETs

Low-frequency (LF) noise in a vertically stacked nanowire (VS-NW) memory device, which is based on the silicon-oxide-nitride-oxide-silicon (SONOS) configuration is characterized in two different operational modes, an inversion-mode and a junctionless-mode (JM). The LF noise showed 1/f -shape behavior regardless of the operational mode and followed the carrier number fluctuation model. With regard to the device-to-device variation and quality degradation of the LF noise after iterative program/erase operations, the five-story JM SONOS memory showed comparatively high immunity arising from its inherent bulk conduction and no-junction feature. Despite the harsh fabrication condition used to construct five-story VS-NW, even the five-story JM SONOS memory exhibited LF noise characteristics comparable to those of one-story JM SONOS memory. Thus, the five-story JM SONOS memory is attractive due to its high-performance capabilities and good scalability.

Ultra-Fast Erase Method of SONOS Flash Memory by Instantaneous Thermal Excitation

An ultra-fast erasing process that acts within 200 ns is demonstrated in a junctionless gate-all-around nanowire silicon-oxide-nitride-oxide-silicon device. Rapid erasing is enabled with the use of instantaneous thermal excitation (TE) through a double-ended gate structure. Charges inside the silicon nitride layer are de-trapped by Joule heating. Moreover, an in-situ self-annealing effect accompanied by the TE erase method is achieved; hence, both the tunnel oxide quality and the retention characteristics are less degraded compared with the conventional Fowler-Nordheim erase method.

First demonstration of a wrap-gated CNT-FET with vertically-suspended channels

Fully wrap-gated carbon nanotube (CNT) transistors with vertically suspended (VS) semiconducting single-walled CNTs, purified up to 99.9%, are demonstrated for the first time. Without a sacrifice of scalability, remarkably enhanced gate controllability and charge transport capabilities were achieved due to the geometrical advantage of the gate-all-around (GAA) structure with multiple channels. The VS channels were formed with the aid of a silicon-processed vertically integrated nanowire frame, offering high completeness and compatibility with silicon processes. This approach will increase the applicability of CNTs toward high-performance emerging materials.

Impact of crystalline damage on a vertically integrated junctionless nanowire transistor

The influence of process-induced defect formation was investigated in a vertically integrated (VI) junctionless-mode field-effect transistor (JL-FET). Compared to the low energy and one-time ion-implantation process to fabricate a single nanowire-based FET, the high-energy and repetitive ion-implantation process for the creation of the VI JL-FET inevitably generates more defects in the crystalline sites. Even after high-temperature rapid thermal annealing, the non-recovered defect sites existing in the interface and silicon channel, as verified by a transmission electron microscopy analysis, lead to the degradation of the electrical performance such as on- and off-state current. Particularly, the abnormal behavior of the off-state current, mostly arising from the gate-induced drain leakage, was analyzed using the experimental results, and supported by the numerical simulation as well.