Sanghoon Hwang

Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an autoswitching encoder for efficient digital processing is also presented. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28mm2 in 0.18μm CMOS technology.

Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18mu m 1-poly 5-metal CMOS technology. The active chip area is 0.79 mm2 and it consumes about 200 mW at 1.8 V power supply. The DNL and INL are within plusmn0.6/plusmn0.6LSB, respectively. The measured result of SNDR is 47.05dB.

A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder

In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed track-and-hold (T/H), a novel one-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18/spl mu/m CMOS occupies an area of 977/spl mu/m /spl times/ 1040/spl mu/m and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.

Design of a 1.8V 6-bit 100MSPS 5mW CMOS A/D Converter with Low Power Folding-Interpolation Techniques

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm2 in 0.18mum CMOS technology

Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8 V, 0.18 mum, 1-poly, 5-metal CMOS technology. It occupies 0.52 mm2 of silicon area with 15.8 mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.

An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction technique

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a resistor-based offset averaging technique, and a one-zero detecting encoder are proposed. The fabricated chip with 0.1 /spl mu/m CMOS occupies an area of 977 /spl mu/m /spl times/ 1040 /spl mu/m and consumes 145mW at 1.8V power supply. The measured DNL is within 0.5LSB, and the measured SNDR is about 34.55dB, when the input frequency is 10MHz at 2GHz sampling frequency.

A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a Novel Folder Reduction Technique

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 pJ/convstep. The active chip occupies an area of 0.28 mm2 in 0.18 mum CMOS technology.

Design of a 1.8V 6bits Low Power F/I CMOS A/D Converter with a Novel Folder-Reduction Technique

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FOM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm2 in 0.18mum CMOS technology

A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing technique

A 10-b 500 MSPS current-steering CMOS digital-to-analog converter with internal termination resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. Further, for the purpose of reducing glitch noise, a novel current switch based on a deglitching circuit is proposed. A 10-b CMOS DAC has been fabricated with a 3 V, 0.35 /spl mu/m technology, and it consumes 45 mW. The measured SFDR (spurious free dynamic range) is about 65 dB, when the input signal is about 8 MHz at 500 MHz clock frequency.

Design of a small area and low power CMOS D/A converter based on the Alpha-Power Law MOSFET model

While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the Alpha-Power Law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100MSPS CMOS current steering Digital-to-Analog Converter (DAC) with the Alpha-Power Law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8 V, 0.18 mum, 1-poly, 5-metal CMOS technology. It occupies 0.52 mm2 of silicon area with 15.8 mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.