Ming-Jiue Yu

Amorphous InGaZnO Thin-Film Transistors Compatible With Roll-to-Roll Fabrication at Room Temperature

High-performance amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are successfully fabricated on a colorless polyimide substrate using a top-gate self-aligned structure. All thin films are deposited by roll-to-roll-compatible sputtering processes at room temperature. The maximum field-effect mobility is 18 cm2/V·s, the threshold voltage is -1.35 V, the subthreshold slope is 0.1 V/decade, and the on/off current ratio is about 105. The results highlight that excellent device performance can be realized in a-IGZO TFTs without compromising manufacturability.

Influence of Passivation Layers on Characteristics of a-InGaZnO Thin-Film Transistors

We investigated the influence of passivation-layer deposition on the characteristics of a-InGaZnO thin-film transistors (TFTs). The threshold voltage (VT) of the TFTs shifted markedly as a result of the mechanical stress induced by the passivation layers above. By adjusting the deposition parameters during the passivation process, the performance of the TFTs can be modulated. The a-InGaZnO TFTs after dual passivation exhibited good performance with a field-effect mobility of 11.35 cm2/V·s, a threshold voltage of 2.86 V, and an on-off ratio of 108.

Effects of Mechanical Strains on the Characteristics of Top-Gate Staggered a-IGZO Thin-Film Transistors Fabricated on Polyimide-Based Nanocomposite Substrates

In this paper, we had successfully implemented flexible top-gate staggered amorphous In-Ga-Zn-O (a-IGZO) thin- film transistors (TFTs) on colorless and transparent polyimide (PI)-based nanocomposite substrates using fully lithographic and etching processes that are compatible with existing TFT mass fabrication technologies. The use of the selectively coated release layer between the nanocomposite PI film and the glass carrier ensured smooth debonding of the plastic substrate after TFT fabrication. The TFTs showed decent performances (with mobility >; 10 cm2/V · s) either as fabricated or as debonded from the carrier glass. By bending the devices to different radii of curvature (from a flat state to an outward bending radius of 5 mm), influences of mechanical strains on the characteristics of flexible a-IGZO TFTs were also investigated. In general, the mobility of the flexible a-IGZO TFT increased with the tensile strain, whereas the threshold voltage decreased with the tensile strain. The variation of the mobility in a-IGZO TFTs versus the strain appeared smaller than those observed for amorphous silicon TFTs.

Flexible Three-Bit-Per-Cell Resistive Switching Memory Using a-IGZO TFTs

This letter proposes a novel high bit density nonvolatile memory using a logic compatible flexible amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) structure fabricated at low temperature. Before electrical forming, the a-IGZO TFT exhibits excellent transistor performance, including an ON/OFF current ratio of 8.8×106, a steep subthreshold slope of 0.14 V/decade, a threshold voltage of 0.55 V, and a maximum field-effect mobility of 2 cm2/Vs. After electrical forming, a three-bit-per-cell resistive switching memory is realized using localized multilevel resistance states at the drain and source bits. Combining dual functionalities to achieve low-cost integration and excellent device characteristics at bending states, the proposed device is promising for future system-on-plastic applications.

Abnormal positive bias stress instability of In-Ga-Zn-O thin-film transistors with low-temperature Al2O3 gate dielectric

Low-temperature atomic layer deposition (ALD) was employed to deposit Al2O3 as a gate dielectric in amorphous In–Ga–Zn–O thin-film transistors fabricated at temperatures below 120 °C. The devices exhibited a negligible threshold voltage shift (ΔVT) during negative bias stress, but a more pronounced ΔVT under positive bias stress with a characteristic turnaround behavior from a positive ΔVT to a negative ΔVT. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive ΔVT, which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al2O3 is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In–Ga–Zn–O channel and induce the negative ΔVT through electron doping with power-law time dependence. A rapid partial recovery of the negative ΔVT after stress is also observed during re...

High-Voltage Amorphous InGaZnO TFT With Al 2 O 3 High-

On-chip high-voltage (HV) power management integrated circuits would deliver smaller form factor, lower system cost, higher power efficiency, and suppressed noise in system-on-chip designs. A reliable HV amorphous-indium- gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology has been presented for potential applications of monolithic 3-D integration on CMOS. By using a process temperature below 200 °C, the instability of positiveand negative-bias stresses can be carefully minimized. The HV a-IGZO TFT with an Al2O3 high-k gate dielectric possesses a high breakdown voltage exceeding 45 V, a high saturation mobility of 11.3 cm2/Vs, and a large ON-/OFF-current ratio of 109. The long-term reliability study projects that the device can be operated at 20 V for ten years without catastrophic dielectric breakdown while maintaining sufficient ON-current.

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To enable monolithic three-dimensional integration of the amorphous In-Ga-Zn-O (a-IGZO) and CMOS technologies, the a-IGZO inverters compatible with the low operating voltage (≤1 V) and process temperature of back-end-of-line CMOS have been investigated. We demonstrated a full-swing depletion-load inverter with a voltage gain up to 24 using a CMOS-compatible operating voltage of 1 V. The drive transistor was realized using a low-voltage enhancement-mode a-IGZO thin-film transistor (TFT) with a steep subthreshold swing of 70 mV/decade and a low threshold voltage of 0.5 V. The load transistor was implemented using a bi-layer a-IGZO channel, where the a-IGZO composition was modulated simply by the oxygen flow rate in a depletion-mode TFT.

Dielectric for Low-Temperature Monolithic 3-D Integration

We reported a novel flexible nonvolatile memory using complete logic-compatible a-IGZO TFTs fabricated at room temperature. The memory device utilized localized and independent resistive switching for high-density two-bit-per-cell and multi-bit-per-cell operations. Combining low-temperature fabrication, low-cost integration, high bit-density, and excellent flexible memory characteristics, this device shows promise for future system-on-plastic applications.

1-V Full-Swing Depletion-Load a-In–Ga–Zn–O Inverters for Back-End-of-Line Compatible 3D Integration

The wide band-gap a-IGZO is a promising channel material to realize high-voltage transistors that can be easily integrated on logic ICs by low-temperature 3D stacking. This monolithic 3D integration would enable on-chip power management to improve power consumption and integration density. We report a high-voltage a-IGZO TFT with the high-k Al2O3 gate dielectric. By using a low-temperature process below 200 °C, excellent transistor characteristics, including a current on/off ratio of 109, steep subthreshold swing of 0.1 V/decade, high breakdown voltage of 45 V, and robust bias stress reliability have been demonstrated.

Multi-bit-per-Cell a-IGZO TFT resistive-switching memory for system-on-plastic applications

Transition metal dichalcogenide (TMD)-based field effect transistors are currently being actively researched as a post-silicon solution for integrated circuits. This paper discusses two of the major challenges: grain size in polycrystalline TMD monolayer films and chemical doping to improve TMD/metal contacts. The characterization techniques and the correlation with device electrical characteristics are investigated.