Ryoung-Han Kim

Low track height standard cell design in iN7 using scaling boosters

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform

This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho and after etch, and variability was characterized both with conventional CD-SEM measurements as well as Hitachi contouring method. After analyzing the patterning of these layers, the impact of variability on potential interconnect reliability was studied by using MonteCarlo and process emulation simulations to determine if current litho/etch performance would meet success criteria for the given platform design rules.

Reticle enhancement techniques toward iN7 metal2

The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent metal layers1. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5. Regarding the metal 2 layer, imec is evaluating two integration approaches: EUV single print and SAQP+EUV Block. Extensive work is reported on both approaches2,3. The work detailed in this paper will deal about the computational work done prior to tape-out for the EUV direct print option. We will discuss the EUV source mask optimization for an ASML NXE:3300 EUV scanner. Afterwards we will shortly touch upon OPC compact modeling and more extensively on OPC itself. Based on the current design rules and MRC, printability checks indicate that only limited process windows are obtained. We propose ways to improve the printability through MRC and design. Applying those changes can potentially lead to a sufficient process window.

Single exposure EUV of 32nm pitch logic structures: patterning performance on BF and DF masks

This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore’s law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back- End of Line (BEoL). 193immersion usage now requires self-aligned and/or multiple patterning technique combinations to enable such critical dimension. On the other hand, EUV insertion investigation shows that 32nm metal pitch is still a challenge but, related to process flow complexity, presents some clear motivations. Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers. In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.

EUVL Gen 2.0: key requirements for constraining semiconductor cost in advanced technology node manufacturing

The constant improvement of critical pitch reduction to enable the next generation semiconductor technology node is the primary driver for innovation in semiconductor industry. Previous researches [1] have shown the benefits of EUVL to bring down the wafer manufacturing cost for imec 7nm technology node. Beyond the technology node (N node) that will use EUV single patterning to enable the critical layers, the critical pitch enablement would require the second generation of EUVL lithography (high NA EUV) or double patterning EUVL(EUVL-DP). In this paper, we have provided a comparison between the two alternatives in terms of cost. We explored patterning options that would enable a costfriendly 5nm logic (N+1 node). The goal is to analyze the alternatives beyond the current 0.33 NA EUVL single patterning limit.

Double patterning at NA 0.33 versus high-NA single exposure in EUV lithography: an imaging comparison

As minimum feature size shrinks to a metal pitch of 21 nm, the current extreme ultra violet (EUV) lithographic tool with a numeric aperture (NA) of 0.33 will face resolution limit for some critical layers. High NA (0.55) EUV with anamorphic optics or EUV double patterning (DP) at 0.33 NA are being considered for the next generation of lithographic technology. Both the high NA EUV system and EUV DP will enhance resolution relative to current EUV single patterning (SP). Nevertheless, in order to be able to compare EUV DP and High NA EUV processes, important lithographic factors including image contrast, mask three dimension (M3D) effects, process variation band, stochastic effects and local critical dimension uniformity need to be investigated to understand their contributions to process variations. This study was carried out using rigorous lithographic model simulations in Sentaurus Lithography, where strong M3D effects in EUVL are computed physically. We have simulated patterns with both isomorphic and anamorphic optical proximity corrections (OPC) using the rigorous model. The study focuses on 3nm node Via layer designs. These vias need to connect to metal features which have pitches of 21 nm. Simulation results using 0.33 NA SP, 0.33 NA DP, and 0.55 NA anamorphic SP are presented. The benefit of using an alternative mask absorber and a thinner resist as well as the impact of stochastic effects have also been explored. Although a 0.55 NA EUV is expected to produce a superior image to 0.33 NA EUV and to have less impact from overlay errors and stochastic effects, an analysis of process margins of 0.33 NA EUV SD and DP versus 0.55 NA anamorphic systems helps to better understand the benefits, challenges and optimal insertion point for introducing High-NA EUV.

IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend

In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.

Design and pitch scaling for affordable node transition and EUV insertion scenario

imec’s DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of 42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell design, integration and patterning specification are discussed.

Directed self-assembly enabled fully self-aligned via processing (Conference Presentation)

Until recent years, dimensional scaling allowed for the fabrication of smaller and faster devices with increasing capacity. Currently, the limited area and the high density of the features in such devices have made self-aligned contacts/vias (SAC or SAV) a standard technique to overcome the decreasing distance between electrically functional elements in integrated circuits. In SAV schemes, the use of hard masks to define the effective transferred patterns allows for more relaxed via patterning conditions and overlay requirements. In this work, we explore a DSA-based fully self-aligned vias (FSAV) flow to further improve on traditional SAV processes. We use directed self-assembly (DSA) of block copolymers (BCP) to generate topographic features between the metal lines, which in combination with SAV, extend the benefits of this method to both X-Y directions, while maximizing the distance between the contacts and the adjacent not-connected metal lines to avoid potential shorts, as shown in Figure 1. In order to achieve this, patterned metal and/or dielectric lines are selectively functionalized using homopolymer brushes, to form a 1:1 chemical nano-pattern of specific surface energy, such that, when a BCP layer is coated and annealed on these samples, each block will align to the metal (or dielectric) lines underneath, as shown on Figure 2. We subsequently use one of the blocks as a template to generate topographic features between the metal lines. In addition, different hard masks are characterized to find the optimal material for the current scheme. Finally, we define the design rules for integration of the proposed flow into electrical devices.