Minsu Jeong

A 9dBm IIP3 direct-conversion satellite broadband tuner-demodulator SOC

A direct-conversion satellite tuner-demodulator IC is realized using 0.18/spl mu/m CMOS technology. The IC down-converts a 950-2150MHz satellite broadcasting signal to base band and demodulates the signal to an MPEG data stream. The IC conforms to both DVB-S and DSS standards. Experimental results show a 9dBm IIP3 while consuming 230mA from 1.8V supply.

A 100mW Dual-Band CMOS Mobile-TV Tuner IC for T-DMB/DAB and ISDB-T

A 0.18mum CMOS dual-band low-IF mobile-TV tuner IC for T-DMB/DAB that supports Band-III and L-band is presented. By modifying a few metals and via masks, the IC can support VHF and UHF bands for ISDB-T partial reception. The chip meets all the specifications of both applications with a sensitivity of <-98dBm while consuming 100 mW from a 1.8V supply and occupying 3.4times3.3mm2

A 2.4-GHz CMOS Driver Amplifier Based on Multiple-Gated Transistor and Resistive Source Degeneration for Mobile WiMAX

A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with two auxiliary transistors extends the linear region further compared with MGTR with single auxiliary transistor. Second, resistive source degeneration significantly suppresses the unwanted 2nd-harmonic feedback effect caused by an inductive source degeneration. A 2.4-GHz differential driver amplifier has been implemented in 0.18 mum CMOS for Mobile WiMAX and Korean WiBro applications. It shows that the linear region with OIP3 of >+20dBm is extended up to an output power of -5 dBm, while achieving a maximum OIP3 of +28 dBm, OPldB of +7.8 dBm, and a power gain of 9.2 dB with dc power consumption of 1.8V and 18.7 mA.

A 43dB ACR low-pass filter with automatic tuning for low-IF conversion DAB/T-DMB tuner IC

This paper provides a channel select low-pass filter with automatic cut-off frequency tuning circuit for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner IC. This filter has 1.58MHz cut-off frequency, 20dB and 65dB stop band attenuation at 1.9MHz and 2.4MHz, respectively. The in-band IIP3 is -8.4dBV and 1dB desensitization is satisfied for 490mVpp interferer at 1.7MHz frequency offset. By using simple automatic tuning technique, less than +/-1.5% cut-off frequency error and more than 40dB adjacent channel rejection (ACR) are obtained. The low-pass filter is fabricated in 0.18/spl mu/m CMOS technology and consumes about 4.5mA with 1.8V power supply.

A High-Efficiency CMOS Power Amplifier Using 2:2 Output Transformer for 802.11n WLAN Applications

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves ?28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

A Fully Integrated Dual-Band WLP CMOS Power Amplifier for 802.11n WLAN Applications

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

A Fully Integrated Dual-Mode CMOS Power Amplifier With an Autotransformer-Based Parallel Combining Transformer

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated with a standard 40-nm CMOS process. In comparison with a parallel combining transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, and does so with a compact die area. With an 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, the fully integrated dual-mode PA achieves 19.7 and 15.7 dBm average output powers with PAEs of 17.1% and 13%, in HP and LP modes, respectively, while satisfying a −25 dB error vector magnitude and spectral mask requirements. Operating the PA in the LP mode can save more than 40% of the current consumption at a 10-dBm average output power when compared with that in the HP mode.