Hiroaki Honjo

A 90nm 12ns 32Mb 2T1MTJ MRAM

Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1–4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of stand-alone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time.

MRAM Cell Technology for Over 500-MHz SoC

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum2, which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cells static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJs cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of todays VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.

High-speed simulator including accurate MTJ models for spintronics integrated circuit design

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used.

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under Vdd=1V. The 1Mb chip with 2.19μm2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

Improvement of Thermal Stability of Magnetoresistive Random Access Memory Device with SiN Protective Film Deposited by High-Density Plasma Chemical Vapor Deposition

Embedded magnetoresistive random access memory (MRAM) with multi-level interconnects necessitates that magnetic tunnel junction (MTJ) devices have a thermal stability of 350 °C or higher during fabrication. We have improved thermal stability of MRAM devices using SiN protective film deposited by high-density plasma chemical vapor deposition (HDP-CVD) at 200 °C. The MTJ devices with HDP-CVD SiN protective film did not degrade after post-annealing at 350 °C, which suggests that the HDP-CVD process reduced oxide metal on the etched surface of the MTJ devices and that the SiN film blocked H2O diffusion from the interlayer dielectric film during post-annealing at 350 °C. We also fabricated a 1-kbit MRAM array and experimentally demonstrated thermal stability at 350 °C.

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

High-speed capability and excellent reliability of a magnetic domain wall (DW) motion device required for embedded memory and logic-in-memory applications were achieved by optimizing the film stack structure of Co/Ni wire. Low-current with high-speed writing, high heat resistance, low error rate, wide operation range for temperature and magnetic field, high retention, and high endurance features were confirmed.

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.