Mitsutoshi Higashi

Studies on electrical performance and thermal stress of a silicon interposer with TSVs

The silicon interposer had been desired to have high Imput/Output (I/O) counts and fine wirings such as the global wiring of devices. High integration of several chips on the silicon interposer will realize a high performance silicon module same as System on Chip (SoC). We previously reported the fabrication process of TSVs and fine Cu wirings on a silicon interposer and the results of reliability test [1] [2]. Furthermore in order to reduce the stress at the 2nd level interconnection, we evaluated Trenched Air Gap (TAG)-TSV, which were fabricated by silicon etching around Cu-TSVs as a stress relief function [3]. In this reports, we focused on the properties of the silicon interposer. We evaluated the electrical performance of TAG-TSVs by measurement of S21 parameter. In addition, in order to obtain the stability of Power/Ground delivery we evaluated the fusing current of the fine Cu wiring and compared with that of Al spatter wiring. Furthermore we reported thermal stress measured with piezoresistive sensor which was mounted on the silicon interposer.

Development of silicon module with TSVs and global wiring (L/S=0.8/0.8µm)

In recent years, in order to achieve high density and high transmission speed between chips, various kinds of silicon modules have been developed.

Warpage control of silicon interposer for 2.5D package application

In order to achieve high speed transmission and large volume data processing, large size silicon-interposer has been required. Warpage caused by the CTE mismatch between a large silicon-interposer and an organic substrate is the most significant problem. In this study, we investigated several warpage control techniques for 2.5D package assembly process. First was assembly process sequence. One is called “chip first process” that is, chips are mounted on Si-interposer at first. The other is called “chip last process” that is, silicon-interposer is mounted on organic substrate at first and chips are mounted on at last. The chip first process successfully processed using conventional mass reflow. By using the chip first process, apparent CTE of a large silicon-interposer become close to that of an organic substrate. Second was the warpage control using underfill resin. We focused on the selection of underfill materials for 0 level assembly. And third was the warpage control technique with Sn-57Bi solder using conventional reflow process. We observed warpage change during simulated reflow process using three-dimensional digital image correlation system (3D-DIC). Sn-57Bi solder joining has been noted as a low temperature bonding methods. It is possible to lower peak temperature 45-90 degree C during reflow compared with using Sn3.0wt%Ag0.5wt%Cu (SAC305). By using Sn-57Bi solder, the warpage after reflow was reduced to 75% of that using SAC305. The full assembly was successfully processed using conventional assembly equipment and processes. The full assembly packages were evaluated by some reliability tests. All samples passed each reliability test.

High density 3D silicon interposer technology development and electrical characterization for high end applications

As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer approach combined with 3D integration technologies opens new possibilities in advanced packaging. Especially for high end applications where several processor needs to communicate together, this approach could enhance the performances of whole systems. However there are many requirements for this type of packaging as: — Thin wafer processing for silicon interposer, -High I/O density between chips and silicon interposer, -Compatibility with CTE mismatch between organic substrate and large silicon interposer. In the first part of this paper the design of the silicon interposer demonstrator successfully processed will be presented as well as the integration schemes with chip and organic substrate. Then, the process flow developed for this application will be commented in order to explain the main technological levels. A dedicated part will focus on silicon interposer bow optimization which is one of the most critical point for mounting. Finally, the electrical performances of each level and of combined chains will be presented and analyzed with some preliminary results of mounting with chips and organic substrate.

Electro-migration behavior in low temperature flip chip bonding

In this report, we investigated electro-migration behavior of two types of low temperature bonding. One was Sn-57 Bi using conventional C4 process. The other was Au-In Transient Liquid Phase bonding (TLP). Electron flow to induce the electro-migration was from substrate side (Ni pad) to chip side (Cu post) with current density of 40000A/cm2 at 150 degree C. In the case of Sn-57 Bi conventional C4 process, Bi quickly migrated to accumulate on the anode side (Cu post) and Sn migrated to the cathode side (substrate Ni pad). And the interconnect resistance increased until about 150 hours. Although this temperature was higher than the melting point of Sn57 Bi solder, there was no electrically break failure and the resistance was stabilized at 80% increase of initial resistance for more than 2800 hours, that was 10 times longer life of the Sn3.0wt%Ag0.5wt%Cu (SAC305) solder joint. From the cross-sectional analyses of Sn-57 Bi solder joints after the test, it was found that Bi layer and intermetallic compound (IMC) behaved as the barriers of the Cu atom migration into Sn solder. In the case of Au-In TLP bonding, remarkable change was not observed in metallic structure. And resistance was stabilized at 0.5% increase of initial for more than 1300 hours. Sn57 Bi solder joining and Au-In TLP bonding are promising candidates for the bonding technique of high density Flip Chip packages and 3D packages.

Study of electro-migration resistivity of micro bump using SnBi solder

There has been a great discussion about electro-migration behavior in semiconductor area. And it has been often discussed that electro-migration behavior of the flip chip package using Sn-Ag bump. However, little study has been done to explore the electro-migration behavior of low temperature solder such as a Sn-Bi solder. In this report, we investigated electro-migration behaviors of micro pillar bump (100 μm diameter) and fine pitch micro bump (25 μm diameter) using Sn57wt%Bi solder. In the case of micro pillar bump, Bi quickly migrated and accumulated on the anode side (Cu pillar) and Sn migrated to the cathode side (substrate pad). And interconnect resistance was quickly increased 80 % from initial during about 150 hours. There was no electrically break failure and it was stabilized at 80% of initial resistance for more than 2800 hours. On the other hand, in the case of fine pitch micro bump, almost of Sn atoms were consumed to form Cu-Sn or Ni-Sn intermetallic compounds (IMCs) after bonding process. The resistance increase was less than 9 %, it is stabilized even for more than 2200 hours and there were no electrically break failure. Additionally, it is evident from electromagnetic field simulation that the maximum current density of the fine pitch micro bump are less than half compared with that of Cu-pillar bumps. Fine pitch micro bump using Sn57 Bi solder is promising candidates for the bonding technology of high performance packages.

Warpage behavior in 2.5D package using Si-interposer

Influence factors of warpage change during assembly process for 2.5D package using silicon-interposer were investigated. Mechanical properties of organic substrate have the dominant influence. In contrast, material properties of U.F. material have little impact.

Electrical and morphological characterization for high integrated silicon interposer and technology transfer from 200 mm to 300mm wafer

To achieve high density and high speed transmission between chips, a silicon interposer with copper (Cu) Through Silicon Vias (TSVs) technologies have been required. In previous papers, we reported process development and integration with 200mm wafer. It has been shown that high aspect ratio TSVs were filled with Cu without any voids. Delamination of dielectric layers did not occur on both side of silicon interposer. Furthermore electrical characterizations such as TSV kelvin resistance, daisy chain resistance between TSVs were reported [1][2]. In this paper, the first part reports morphological data for micro bumps. We focused on the characterization of Cu/Ni/Solder micro bumps after integrations of the silicon interposer process flow by Scanning Electron Microscope (SEM) cross section and Nano-Auger spectroscopy. The second part describes the electrical data for the silicon interposer. We focused on the fusion current tests and high frequency properties (RF test) of TSVs. The last part reports on the technology transfer from 200mm to 300mm wafer line in order to achieve low cost silicon interposers. Based on technical data from studies and process integration on 200mm line, processes are transferred to 300mm wafer line and first electrical and morphological characterizations are introduced.

Cost and performance effective silicon interposer and Vertical Interconnect for 3D ASIC and memory integration

To enable three-dimensional (3D) ASIC and memory integration, large-size silicon interposer is a critical technology [1]. Currently most silicon interposers are manufactured by wafer foundries and are limited in size by the wafer lithographic processing. In this study, manufacturing of cost- and performance-effective, large-size silicon interposers are investigated. The existing supply chain and infrastructure of high-performance flip-chip packaging substrates is leveraged. A 3D System-in-Package (SiP) is designed and manufactured that includes a large-size silicon interposer with Through-Silicon-Vias (TSV) and Cu wiring layers on both sides of the silicon interposer. To develop the assembly process for the 3D SiP, thermal deformation of each constituent component is analyzed using metrological techniques such as Digital Image Correlation (DIC). With the assembly process developed, an ASIC die is attached on top of the silicon interposer while two smaller memory dice are attached to the bottom of the silicon interposer with micro-bump interconnection. The 3D IC stack is then assembled on an organic package substrate with two Vertical Interconnect Spacers (VISs) and “regular” solder bumps so the bottom dice can be accommodated without any interference to the planar organic substrate. The completed 3D SiP module is finally assembled on a test board using a lead-free surface mount process. Thermo-mechanical reliability of the 3D SiP assembly is studied using temperature cycling testing. Both the thermal deformation analysis and stress testing results are used to gain insights into the 3D IC technology and to enable ASIC and memory integration for next generation high-performance network systems.