Masahiro Sunohara

Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

In order to achieve high density and high performance package, through silicon vias (TSVs) technology has been desired. Our purpose is the development of silicon interposer which has TSVs and fine multilayer Cu wiring on both side. Since silicon substrate has a quite flat and smooth surface, it can be expected to form fine wiring such as global layer of device. Furthermore, silicon interposer can be expected to show high reliability of bump connection for the reason of the same coefficient of thermal expansion (CTE) with silicon devices. In this paper, elemental technologies such as interconnection of TSV, fabrication of fine wiring, and evaluation of interlayer dielectric are reported. Finally, the application of silicon interposer such as silicon module and inorganic-organic hybrid substrate, are described. As further evolution systems, a substrate with micro channel and substrate less package are proposed.

Studies on electrical performance and thermal stress of a silicon interposer with TSVs

The silicon interposer had been desired to have high Imput/Output (I/O) counts and fine wirings such as the global wiring of devices. High integration of several chips on the silicon interposer will realize a high performance silicon module same as System on Chip (SoC). We previously reported the fabrication process of TSVs and fine Cu wirings on a silicon interposer and the results of reliability test [1] [2]. Furthermore in order to reduce the stress at the 2nd level interconnection, we evaluated Trenched Air Gap (TAG)-TSV, which were fabricated by silicon etching around Cu-TSVs as a stress relief function [3]. In this reports, we focused on the properties of the silicon interposer. We evaluated the electrical performance of TAG-TSVs by measurement of S21 parameter. In addition, in order to obtain the stability of Power/Ground delivery we evaluated the fusing current of the fine Cu wiring and compared with that of Al spatter wiring. Furthermore we reported thermal stress measured with piezoresistive sensor which was mounted on the silicon interposer.

Development of silicon module with TSVs and global wiring (L/S=0.8/0.8µm)

In recent years, in order to achieve high density and high transmission speed between chips, various kinds of silicon modules have been developed.

Warpage control of silicon interposer for 2.5D package application

In order to achieve high speed transmission and large volume data processing, large size silicon-interposer has been required. Warpage caused by the CTE mismatch between a large silicon-interposer and an organic substrate is the most significant problem. In this study, we investigated several warpage control techniques for 2.5D package assembly process. First was assembly process sequence. One is called “chip first process” that is, chips are mounted on Si-interposer at first. The other is called “chip last process” that is, silicon-interposer is mounted on organic substrate at first and chips are mounted on at last. The chip first process successfully processed using conventional mass reflow. By using the chip first process, apparent CTE of a large silicon-interposer become close to that of an organic substrate. Second was the warpage control using underfill resin. We focused on the selection of underfill materials for 0 level assembly. And third was the warpage control technique with Sn-57Bi solder using conventional reflow process. We observed warpage change during simulated reflow process using three-dimensional digital image correlation system (3D-DIC). Sn-57Bi solder joining has been noted as a low temperature bonding methods. It is possible to lower peak temperature 45-90 degree C during reflow compared with using Sn3.0wt%Ag0.5wt%Cu (SAC305). By using Sn-57Bi solder, the warpage after reflow was reduced to 75% of that using SAC305. The full assembly was successfully processed using conventional assembly equipment and processes. The full assembly packages were evaluated by some reliability tests. All samples passed each reliability test.

Thermal characterization of bare-die stacked modules with Cu through-vias

This paper describes the thermal characteristics of three dimensional (3-D) modules where four bare-dies with Cu through-vias are vertically stacked and electrically connected through the Cu-vias and the metal bumps. To realize more accurate thermal analysis for the 3D-modules in the earlier stage of the process development, a series of simple thermal resistance measurements by laser-flash method and parametric numerical analyses have been carried out. First, the thermal effects of the interface between two layers were quantified on the basis of the results of the laser-flash method. Second, using experimental interfacial thermal resistance, the thermal conduction analyses for 3D-modules were carried out. The key parameters governing the thermal performance of bare-die stacked modules and the design guideline of the thermal bumps are presented.

Development of interconnect technologies for embedded organic packages

Recently various technologies have been developed for next generation packaging. Requirements are the minimization of components, high-density, high-speed cn, performance and low-cost productivity. In ordet to satisfy these requirements, we have examined to embed components into the organic substrate. Objective of our embedded packages is low cost manufacturing using the conventional build-up substrate process and materials. (a)MCMtype (b) Chip stack type

Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI

The three-dimensional (3D) chip stacking technology has been developed extensively recently for the next generation packaging technology. The technology includes thorough electrode fabrication, wafer thinning, wafer backside processing, testing, and chip stacking. Wafer thinning and wafer backside processing are important technologies among them, because these technologies accommodate small and thin form factor, enable thin chip stacking, and enhances electrical and mechanical reliability of the stacked module. In this paper, novel technologies of wafer thinning and wafer backside processes that include insulation film formation and bumping on the backside of the thinned wafer are described.

High density 3D silicon interposer technology development and electrical characterization for high end applications

As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer approach combined with 3D integration technologies opens new possibilities in advanced packaging. Especially for high end applications where several processor needs to communicate together, this approach could enhance the performances of whole systems. However there are many requirements for this type of packaging as: — Thin wafer processing for silicon interposer, -High I/O density between chips and silicon interposer, -Compatibility with CTE mismatch between organic substrate and large silicon interposer. In the first part of this paper the design of the silicon interposer demonstrator successfully processed will be presented as well as the integration schemes with chip and organic substrate. Then, the process flow developed for this application will be commented in order to explain the main technological levels. A dedicated part will focus on silicon interposer bow optimization which is one of the most critical point for mounting. Finally, the electrical performances of each level and of combined chains will be presented and analyzed with some preliminary results of mounting with chips and organic substrate.

Electrical and morphological characterization for high integrated silicon interposer and technology transfer from 200 mm to 300mm wafer

To achieve high density and high speed transmission between chips, a silicon interposer with copper (Cu) Through Silicon Vias (TSVs) technologies have been required. In previous papers, we reported process development and integration with 200mm wafer. It has been shown that high aspect ratio TSVs were filled with Cu without any voids. Delamination of dielectric layers did not occur on both side of silicon interposer. Furthermore electrical characterizations such as TSV kelvin resistance, daisy chain resistance between TSVs were reported [1][2]. In this paper, the first part reports morphological data for micro bumps. We focused on the characterization of Cu/Ni/Solder micro bumps after integrations of the silicon interposer process flow by Scanning Electron Microscope (SEM) cross section and Nano-Auger spectroscopy. The second part describes the electrical data for the silicon interposer. We focused on the fusion current tests and high frequency properties (RF test) of TSVs. The last part reports on the technology transfer from 200mm to 300mm wafer line in order to achieve low cost silicon interposers. Based on technical data from studies and process integration on 200mm line, processes are transferred to 300mm wafer line and first electrical and morphological characterizations are introduced.