Mohamed Hassan Abu-Rahma

A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations

The increase of statistical variations in advanced nanometer CMOS technologies poses a major challenge for digital circuit design. In this paper, we study the impact of random variations on the delay variability of a gate and derive simple and scalable statistical models to effectively evaluate delay variations in the presence of within-die variations. The derived models are verified and compared to Monte Carlo SPICE simulations using industrial 90-nm technology. This paper provides new design insight and highlights the importance of accounting for the effect of input slew on delay variations, particularly at lower supply voltages. We also show that, for a given supply voltage, there is an optimum input slew that minimizes the relative delay variation of the gate. We present conditions to achieve this minimum. The derived analytical models account for the impact of supply voltage and output loading and can be used in early design cycle. These results are particularly important for variation-tolerant design in nanometer technologies, particularly in low-power and low-voltage operation.

A methodology for statistical estimation of read access yield in SRAMs

The increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. This is aggravated by the strong demand for lower cost and power consumption, higher performance and density which complicates SRAM design process. In this paper, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow enables early SRAM yield predication and performance/power optimization in the design time, which is important for SRAM in nanometer technologies. The methodology is verified using measured silicon yield data from a 1 Mb memory fabricated in an industrial 45 nm technology.

Leakage current variability in nanometer technologies

The dramatic increase in leakage current coupled with the large increase in variability in highly scaled CMOS technologies, pose a major challenge for future IC design. Leakage variability can not be neglected any more, due to the increase of leakage power percentage in modern ICs. In this paper, the main sources of variations and how they impact leakage current are discussed. Design guidelines to reduce variability based on several leakage reduction techniques are also presented. It is shown that reverse body bias technique increases leakage variability due to its deteriorating effect on drain-induced barrier lowering (DIBL). This paper highlights the need for further efforts in the area of statistical leakage estimation, as well as variation tolerant circuit techniques.

Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS

Random variations play a critical role in determining SRAM yield, by affecting both the bitcell and the read sense amplifiers (SA). In this work, a process control monitor for SRAM SA offset is proposed and implemented in 28nm LP CMOS technology. The monitor provides accurate measurement of SA offset from a large sample size and accounts for all proximity effects that may affect the SA offset. The all-digital design of the monitor makes it adequate for low voltage testing, high speed data collection, and ease of migration to newer technologies. Detailed measurement results are provided for two of the most commonly used sense amplifiers at different supply and temperature conditions. Statistical yield estimation using the measured sense amplifier offset shows good correlation with measured yield for a 512Kb SRAM. The monitor is a critical part of SRAM silicon yield validation, which is becoming of increasing importance with technology scaling, and the significant increase in random variations.

A robust single supply voltage SRAM read assist technique using selective precharge

In this paper, we present a new read assist technique for SRAM to improve bitcell read stability. The new technique utilizes selective precharge where different parts of the bitlines are precharged to VDD or GND. Using charge sharing, the required value of bitline voltage can be precisely set to increase bitcellspsila SNM, while using only one supply voltage. A 512 kb memory was designed to demonstrate this technique in an industrial 45 nm technology. Results show large improvement in SNM and high robustness against process variations. In addition, the proposed technique reduces the memory access time compared to the conventional approach. Moreover, the proposed technique demonstrates higher operating margin which makes it an attractive option to deal with SRAM read stability in nanometer technologies.

Variability in VLSI Circuits: Sources and Design Considerations

Process variations are becoming of increasing importance in nanometer CMOS regime. This paper reviews the challenges associated with variability and variation-tolerant design in nanometer CMOS. It highlights how design decisions, circuit techniques, and architecture decisions are modified to address the difficulties posed by the large increase in process variations.

Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth Control

Embedded SRAM dominates modern SoCs, and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, the large increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. In the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operations and meet yield targets. In this paper, we propose a new architecture that significantly reduces the array switching power for SRAM. The proposed architecture combines built-in self-test and digitally controlled delay elements to reduce the wordline pulsewidth for memories while ensuring correct read operations, hence reducing the switching power. Monte Carlo simulations using a 1-Mb SRAM macro in an industrial 45-nm technology are used to verify the power saving for the proposed architecture. For a 48-Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it an attractive solution for 45-nm-and-below technologies.

Accurate projection of V ccmin by modeling “dual slope” in FinFET based SRAM, and impact of long term reliability on end of life V ccmin

Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin is required to meet the high target yield because the SRAM yield according to Vcc scaling shows “dual slope”. In this paper, the root causes of “dual slope” are analyzed. Both side effect of SRAM bitcell on the yield is also considered to accurately project Vccmin, which results in 40mV increase of Vccmin to meet 99% target yield for 32nm HK/MG planar 1M SRAM. The “dual slope” effect on the yield is compared for 32nm HK/MG planar and FinFET 32M SRAMs with high (HD) and low doping (LD). Under the “dual slope” effect, the channel length adjustment method for pass gate transistor is proposed to reduce Vccmin of FinFET SRAM. When the number of finis is 1∶2∶2(=PU∶PG∶PD), HD and LD 32M FinFET SRAMs improve Vccmin by 370mV and 500mV, respectively, compared to 32M planar counterparts using the proposed the channel length adjustment method. Effect of NBTI and PBTI on Vccmin is also investigated. BTI degradation is greatly dependent on HK thickness and surface plane orientation of FinFET. End of Life (EOL) Vccmin optimization therefore requires careful selection of HK thickness and surface orientation.

Variability in Nanometer Technologies and Impact on SRAM

In recent technologies, there is a high demand to integrate large embedded memories in microprocessors and SoCs. In addition, SRAM bitcell area scaling continues to follow an aggressive 50 % reduction each technology node. Technology scaling and the reduction in device sizes increase variations, which have a strong impact on SRAM operation. In this chapter, we review different types of variations that affect SRAM. We start by presenting the SRAM scaling trends in Sect. 2.1. Next, in Sects. 2.2–2.5, we briefly review sources of variability in nanometer CMOS technology including device, interconnect, and environmental variations. The impact of variations on SRAM operation is presented in Sect. 2.6. Due to the similarities between SRAM and logic circuits, techniques to deal with variations logic circuits are presented in Sect. 2.7.

Leakage power profiling and leakage power reduction using DFT hardware

In a CMOS logic circuit, the leakage power dissipated depends on the state of the design. In this paper we propose a novel technique to use the Q-gating logic that are added to reduce power during shift to also reduce leakage power during functional standby mode of the circuit. First, we propose leakage-aware test (λ-test) vector generation that can be used to profile leakage power consumed by the circuit. This is used to identify blocks that drains excessive standby leakage power. We also propose a new partial Q-gating technique that uses the λ-test to determine the subset of flops that should be gated-off to achieve maximum simultaneous reduction in shift mode dynamic power and standby mode leakage power. A fast, test relaxation and test cube merging algorithm is used for this purpose. Experiments conducted on ISCAS and ITC benchmarks show up to 43.6% reduction in leakage power. For the partial gated design, we obtained up to 15.3% leakage power reduction and up to 6.1×reduction in shift power.