Sei-Seung Yoon

Semiconductor memory device having self-refresh and back-bias circuitry

Multi-bank memory devices having common standby voltage generator for powering a plurality of memory array banks in response to memory array bank enable signals

Voltage boosting circuits having backup voltage boosting capability

Internal clock signal delay circuit and method for delaying internal clock signal in semiconductor device

Method and apparatus for controlling column select lines in a synchronous memory device

Boosting voltage circuit used in active cycle of a semiconductor memory device

Integrated circuit devices having improved internal voltage generators which reduce timing skew in buffer circuits therein

Semiconductor memory using low power supply voltage

Integrated circuits including voltage-controllable power supply systems that can be used for low supply voltage margin testing and related methods

Integrated power supply voltage generators having reduced susceptibility to parasitic latch-up during set-up mode operation